5AGXBA1D4F31C4N Altera Corporation, 5AGXBA1D4F31C4N Datasheet - Page 4

• Manufacturer Part Number: 5AGXBA1D4F31C4N
• Description: FPGA - Field Programmable Gate Array FPGA - Arria V GX 2830 LABS 416 IOs
• Manufacturer: Altera Corporation
• Series: Arria V GXr

Specifications of 5AGXBA1D4F31C4N

• Rohs: yes
• Number Of Logic Blocks: 2830
• Number Of I/os: 416
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.2 V to 1.8 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-896
• Distributed Ram: 8463 kbit
• Minimum Operating Temperature: 0 C

AV-51001
4
Arria V Device Overview
2013.01.11
Feature
Description
External Memory
Memory interfaces with low latency:
Interface
Hard memory controller-up to 1.066 Gbps
Soft memory controller-up to 1.6 Gbps
Low-power
600 Mbps to 12.5 Gbps integrated transceiver speed
high-speed serial
Less than 105 mW per channel at 6 Gbps, less than 165 mW per channel at 10 Gbps,
interface
and less than 170 mW per channel at 12.5 Gbps
Transmit pre-emphasis and receiver equalization
Dynamic partial reconfiguration of individual channels
Physical medium attachment (PMA) with soft PCS that supports 9.8304 Gbps CPRI
(Arria V GT and ST only)
PMA with hard PCS that supports up to 9.8 Gbps CPRI (Arria V GZ only)
Hard PCS that supports 10GBASE-R and 10GBASE-KR (Arria V GZ only)
HPS
Dual-core ARM Cortex-A9 MPCore processor-up to 800 MHz maximum frequency
with support for symmetric and asymmetric multiprocessing
(Arria V SX and ST
Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0
devices only)
On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller,
NAND flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART,
serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO interfaces
System peripherals—general-purpose timers, watchdog timers, direct memory access
(DMA) controller, FPGA configuration manager, and clock and reset managers
On-chip RAM and boot ROM
HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight
HPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves in
the HPS, and vice versa
FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to
the multiport front end (MPFE) of the HPS SDRAM controller
™
ARM CoreSight
JTAG debug access port, trace port, and on-chip trace storage
Configuration
Tamper protection-comprehensive design protection to protect your valuable IP
investments
Enhanced advanced encryption standard (AES) design security features
CvP
Partial and dynamic reconfiguration of the FPGA
Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP)
x8, x16, and x32 (Arria V GZ) configuration options
Remote system upgrade
Arria V Device Overview
Altera Corporation