AD9508/PCBZ Analog Devices, AD9508/PCBZ Datasheet

AD9508/PCBZ

Manufacturer Part Number

AD9508/PCBZ

Description

Clock & Timer Development Tools 1

Manufacturer

Analog Devices

Type

Clock Buffersr

Datasheet

1.AD9508PCBZ.pdf (40 pages)

Specifications of AD9508/PCBZ

Rohs

yes

Product

Evaluation Boards

Tool Is For Evaluation Of

AD9508

Frequency

250 MHz, 1.65 GHz

Operating Supply Voltage

6 V

Description/function

High performance 1

Interface Type

I2C, SPI, USB

Factory Pack Quantity

Current page: 1 of 40
Download datasheet (838Kb)

Data Sheet

FEATURES

1.65 GHz differential clock inputs/outputs

10-bit programmable dividers, 1 to 1024, all integers

Up to 4 differential outputs or 8 CMOS outputs

Pin strapping capability for hardwired programming at

<115 fs rms broadband random jitter (see Figure 25)

Additive output jitter: 41 fs rms typical (12 kHz to 20 MHz)

Excellent output-to-output isolation

Automatic synchronization of all outputs

Single 2.5 V/3.3 V power supply

Internal LDO (low drop-out) voltage regulator for enhanced

Phase offset select for output-to-output coarse delay adjust

3 programmable output logic levels, LVDS, HSTL, and CMOS

Serial control port (SPI/I

Space-saving 24-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

GENERAL DESCRIPTION

The

emphasizes low jitter to maximize system performance. This

device benefits applications like clocking data converters with

demanding phase noise and low jitter requirements.

There are four independent differential clock outputs, each with

various types of logic levels available. Available logic types

include LVDS (1.65 GHz), HSTL (1.65 GHz), and 1.8 V CMOS

(250 MHz). In 1.8 V CMOS output mode, the differential output

becomes two CMOS single-ended signals. The CMOS outputs

are 1.8 V logic levels, regardless of the operating supply voltage.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

power-up

power supply immunity

AD9508

provides clock fanout capability in a design that

C) or pin-programmable mode

Document Feedback

1.65 GHz Clock Fanout Buffer with

Output Dividers and Delay Adjust

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

Each output has a programmable divider that can be bypassed

or be set to divide by any integer up to 1024. In addition, the

AD9508

outputs.

The device can also be pin programmed for various fixed

configurations at power-up without the need for SPI or I2C

programming.

The

a either a single 2.5 V or 3.3 V supply. The temperature range is

−40°C to +85°C.

SCLK/SCL/SC0

SDIO/SDA/S1

AD9508

SDO/S3

supports a coarse output phase adjustment between the

CS/C2

CLK

FUNCTIONAL BLOCK DIAGRAM

is available in a 24-lead LFCSP and operates from

AD9508

PIN CONTROL

SPI/I

INTERFACE

CONTROL

C/PINS

Figure 1.

RESET

SYNC

DIV/Φ

AD9508

www.analog.com

OUT0

OUT1

OUT2

OUT3

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