AD9508/PCBZ Analog Devices, AD9508/PCBZ Datasheet - Page 29

• Manufacturer Part Number: AD9508/PCBZ
• Description: Clock & Timer Development Tools 1
• Manufacturer: Analog Devices
• Type: Clock Buffersr

Specifications of AD9508/PCBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9508
• Frequency: 250 MHz, 1.65 GHz
• Operating Supply Voltage: 6 V
• Description/function: High performance 1
• Interface Type: I2C, SPI, USB
• Factory Pack Quantity: 1

Data Sheet
Table 20. Serial Control Port Timing
Parameter
t
t
t
t
t
t
t
t
I
The I
pins and is a de facto standard throughout the I
However, its disadvantage is the programming speed, which is
400 kbps maximum. The
the I2C fast mode standard; therefore, it supports both the 100 kHz
standard mode and 400 kHz fast mode. Fast mode imposes a glitch
tolerance requirement on the control signals; that is, the input
receivers ignore pulses of less than 50 ns duration.
The
a serial clock line (SCL). In an I2C bus system, the
connected to the serial bus (data bus SDA and clock bus SCL)
as a slave device; that is, no clock is generated by the AD9508.
The
traditional 8-bit memory addressing.
The
the I
address that is transmitted as part of an I
device that has a matching slave address responds to subsequent
I
addresses.
I
Table 21 provides a summary of the various I
used in the protocol.
Table 21. I
Abbreviation
S
Sr
P
ACK
NACK
W
A
R
2
DS
DH
CLK
S
C
HIGH
LOW
DV
2
2
C commands. Table 16 lists the supported device slave
C Bus Characteristics
C SERIAL PORT OPERATION
E
AD9508
AD9508
AD9508
2
2
C bus. These slave devices are accessed via a 7-bit slave
C interface has the advantage of requiring only two control
2
C Bus Abbreviation Definitions
I2C port consists of a serial data line (SDA) and
uses direct 16-bit memory addressing rather than
allows up to four unique slave devices to occupy
Description
Setup time between data and the rising edge of SCLK
Hold time between data and the rising edge of SCLK
Period of the clock
Setup time between the
Setup time between the SCLK rising edge and
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 51)
AD9508
Definition
Start
Repeated start
Stop
Acknowledge
No acknowledge
Write
Read
I2C port design is based on
2
C packet. Only the
C S
A
2
C abbreviations
E
A
falling edge and the SCLK rising edge (start of the communication cycle)
2
C industry.
AD9508
is
Rev. A | Page 29 of 40
C S
A
E
A
rising edge (end of the communication cycle)
The transfer of data is shown in Figure 54. One clock pulse is
generated for each data bit transferred. The data on the SDA
line must be stable during the high period of the clock. The
high or low state of the data line can change only when the
clock signal on the SCL line is low.
SDA
Start/stop functionality is shown in Figure 55. The start condition
is characterized by a high-to-low transition on the SDA line while
SCL is high. The start condition is always generated by the master
to initialize a data transfer. The stop condition is characterized
by a low-to-high transition on the SDA line while SCL is high.
The stop condition is always generated by the master to terminate
a data transfer. Every byte on the SDA line must be eight bits long.
Each byte must be followed by an acknowledge bit; bytes are sent
MSB first.
The acknowledge bit (ACK) is the ninth bit attached to any
8-bit data byte. An acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has been received. The acknowledge bit is communicated
by pulling the SDA
each 8-bit data byte (see Figure 56).
The no acknowledge bit (
8-bit data byte. The receiving device (receiver) always generates
the no acknowledge bit to inform the transmitter that the byte
has not been received. The no acknowledge bit is communi-
cated by leaving the SDA line high during the ninth clock pulse
after each 8-bit data byte.
SCL
DATA VALID
DATA LINE
STABLE;
l
ine low during the ninth clock pulse after
Figure 54. Valid Bit Transfer
N ACK
A
ALLOWED
OF DATA
CHANGE
) is the ninth bit attached to any
A
AD9508