AD9508/PCBZ Analog Devices, AD9508/PCBZ Datasheet - Page 35

• Manufacturer Part Number: AD9508/PCBZ
• Description: Clock & Timer Development Tools 1
• Manufacturer: Analog Devices
• Type: Clock Buffersr

Specifications of AD9508/PCBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9508
• Frequency: 250 MHz, 1.65 GHz
• Operating Supply Voltage: 6 V
• Description/function: High performance 1
• Interface Type: I2C, SPI, USB
• Factory Pack Quantity: 1

Data Sheet
OUT1 FUNCTIONS (REGISTER 0x1B TO REGISTER 0x20)
Table 29. Divide Ratio and Phase
Address
0x1B
0x1C
0x1D
0x1E
Table 30. Output Driver, Power Down, and Sync
Address
0x1F
0x20
Bits
[7:0]
[7:2]
[1:0]
[7:0]
[7:3]
[2:0]
Bits
7
6
[5:4]
[3:1]
0
7
[6:5]
[4]
[3:2]
[1:0]
Bit Name
OUT1 Divide Ratio[7:0]
Reserved
OUT1 Divide Ratio[9:8]
OUT1 Phase[7:0]
Reserved
OUT1 Phase[10:8]
Bit Name
PD_1
SYNCMASK1
OUT1 Driver Phase[1:0]
OUT1 Mode[2:0]
Reserved
EN_CMOS_1P
CMOS_1P_PHASE[1:0]
EN_CMOS_1N
CMOS_1N_PHASE[1:0]
Reserved
Description
Channel 1 divide ratio, Bits[7:0]
0x00 = default
Channel 1 divide ratio, Bits[9:8]
Channel 1 divider phase, Bits[7:0]
0x00 = default
Channel 1 divider phase, Bits[9:8]
Description
Channel 1 power-down
Setting this bit masks Channel 1 from the output sync function
0 = Channel 1 is synchronized during output sync (default)
1 = Channel 1 is excluded from an output sync
These bits determine the phase of the OUT1 driver
00 = force high
01 = noninverting (default)
10 = inverting
11 = force low
These bits determine the OUT1 driver mode
000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)
001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)
010 = LVDS 1 × 3.5 mA (default)
011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)
100 = HSTL 1 × 3.5 mA (normal amplitude)
101 = HSTL 2 × 3.5 mA (double amplitude)
110 = high-Z/CMOS
111 = high-Z/CMOS
0b = default
Setting this bit enables the OUT1P CMOS driver
0 = disables the OUT1P CMOS driver (default)
1 = enables the OUT1P CMOS driver
These bits determine the phase of the OUT1P CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
Setting this bit enables the OUT1N CMOS driver
0 = disables the OUT1N CMOS driver (default)
1 = enables the OUT1N CMOS driver
These bits determine the phase of the OUT1N CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
00b = default
Rev. A | Page 35 of 40
AD9508