MT46H8M16LFCF-10 IT TR Micron Technology Inc, MT46H8M16LFCF-10 IT TR Datasheet
MT46H8M16LFCF-10 IT TR
Specifications of MT46H8M16LFCF-10 IT TR
Related parts for MT46H8M16LFCF-10 IT TR
MT46H8M16LFCF-10 IT TR Summary of contents
Page 1
Mobile DDR SDRAM MT46H8M16LF – 2 Meg Banks For the latest data sheet, refer to Micron’s Web site: Features • +1.8V ±0. • Bidirectional data strobe per byte of data ...
Page 2
Table of Contents Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
List of Figures Figure 1: 60-Ball VFBGA Assignment (Top View ...
Page 4
List of Tables Table 1: Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
... Part Number MT46H8M16LFCF-75 MT46H8M16LFCF-75IT MT46H8M16LFCF-10 MT46H8M16LFCF-10IT FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s new FBGA Part Marking Decoder makes it easier to understand this part marking. Visit the Web site at www ...
Page 6
... PDF: 09005aef8199c1ec/Source: 09005aef81a19319 MT46H8M16LF_1.fm - Rev. K 7/07 EN 128Mb: 8 Meg x 16 Mobile DDR SDRAM BANK3 BANK2 BANK1 12 BANK0 ROW- 12 ROW- BANK0 ADDRESS MUX MEMORY 4,096 LATCH ARRAY AND (4,096 x 256 x 32) DECODER SENSE AMPLIFIERS 8,192 I/O GATING DM MASK LOGIC BANK CONTROL LOGIC 256 ...
Page 7
... Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ or WRITE commands, to select one location out of the memory array in the respective bank. During a PRECHARGE command, A10 determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH) ...
Page 8
... Functional Description The 128Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,271,728-bits internally configured as a quad-bank DRAM. Each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. The 128Mb Mobile DDR SDRAM uses a double data rate architecture to achieve high- speed operation ...
Page 9
... LOAD MODE REGISTER command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again. Reprogramming the standard mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation ...
Page 10
The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. Burst Type ...
Page 11
Table 5: Burst Definition Burst Length Figure 4: CAS Latency CK# COMMAND DQS CK# COMMAND DQS Notes the cases shown. 2. Shown with nominal PDF: 09005aef8199c1ec/Source: 09005aef81a19319 MT46H8M16LF_1.fm - Rev. K 7/07 ...
Page 12
... Because the Mobile DDR SDRAM is designed for use in smaller systems that are mostly point to point, an option to control the drive strength of the output buffers is available. Drive strength should be selected based on the expected loading of the memory bus. Bits A5 and A6 of the extended mode register can be used to select the driver strength of the DQ outputs ...
Page 13
Figure 5: Extended Mode Register BA1 BA0 E13 E12 E12 Mode Register Definintion E13 0 0 Base Mode Register 1 0 Reserved 1 0 Extended Mode Register 1 1 Reserved E6–E0 E11 E10 ...
Page 14
Figure 6: Clock Stop Mode CK# CKE COMMAND Address DQ, DQS Notes: 1. Prior to Ta1, the device is in clock stop mode. To exit, at least one NOP is required before any valid command. 2. Any valid command is ...
Page 15
Commands Table 6 and Table 7 provide quick references of available commands. This is followed by a written description of each command. Three additional Truth Tables (Table 8 on page 42, Table 9 on page 43, and Table 10 on ...
Page 16
... WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coinci- dent with the data given DM signal is registered LOW, the corresponding data will be written to memory ...
Page 17
READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines ...
Page 18
SELF REFRESH The SELF REFRESH command can be used to retain data in the Mobile DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the Mobile DDR SDRAM retains data without ...
Page 19
Operations Bank/row Activation Before any READ or WRITE commands can be issued to a bank within the Mobile DDR SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank ...
Page 20
Figure 8: Example: Meeting T0 T1 CK# CK COMMAND ACT NOP A0-A11 Row BA0, BA1 Bank x READs READ bursts are initiated with a READ command, as shown in Figure 9 on page 21. The starting column and bank addresses ...
Page 21
Figure 9: READ Command CK# CK CKE CS# RAS# CAS# WE# A0–A9 A11 A10 BA0 Column Address BA = Bank Address Enable Auto Precharge DIS AP = Disable Auto Precharge PDF: 09005aef8199c1ec/Source: 09005aef81a19319 MT46H8M16LF_1.fm - ...
Page 22
Figure 10: READ Burst CK# COMMAND ADDRESS DQS CK# COMMAND ADDRESS DQS DQ Notes OUT Shown with nominal PDF: 09005aef8199c1ec/Source: 09005aef81a19319 MT46H8M16LF_1.fm - Rev. K 7/07 EN 128Mb: 8 Meg x 16 Mobile ...
Page 23
Figure 11: Consecutive READ Bursts CK# COMMAND ADDRESS DQS DQ CK# COMMAND COMMAND ADDRESS ADDRESS DQS DQ Notes OUT the cases shown (applies for bursts well ...
Page 24
Figure 12: Nonconsecutive READ Bursts CK# COMMAND ADDRESS DQS CK# COMMAND ADDRESS DQS Notes OUT the cases shown (applies for bursts well the BST command shown ...
Page 25
Figure 13: Random READ Accesses CK# COMMAND ADDRESS DQS CK# COMMAND COMMAND ADDRESS ADDRESS DQS Notes OUT the cases shown (applies for bursts well the BST ...
Page 26
Figure 14: Terminating a READ Burst COMMAND ADDRESS COMMAND ADDRESS Notes OUT 2. Only valid for and Shown with nominal 4. BST = BURST TERMINATE command; page remains open. 5. CKE ...
Page 27
Figure 15: READ-to-WRITE COMMAND ADDRESS DQS CK# COMMAND ADDRESS DQS Notes OUT the cases shown (applies for bursts well the BST command shown ...
Page 28
Figure 16: READ-to-PRECHARGE COMMAND ADDRESS COMMAND ADDRESS Notes OUT interrupted burst Shown with nominal 4. READ-to-PRECHARGE equals 2 clocks, which allows 2 data pairs of data-out READ ...
Page 29
WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 17 on page 30. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. ...
Page 30
Figure 17: WRITE Command CK# CK CKE CS# RAS# CAS# WE# A0–A8 A11 A10 BA0,1 Note: DIS AP = Disable Auto Precharge Enable Auto Precharge BA = Bank Address CA = Column Address PDF: 09005aef8199c1ec/Source: 09005aef81a19319 MT46H8M16LF_1.fm ...
Page 31
Figure 18: WRITE Burst COMMAND ADDRESS t DQSS (NOM) t DQSS (MIN) t DQSS (MAX) Notes uninterrupted burst shown. 3. A10 is LOW with the WRITE command (auto precharge is disabled). PDF: ...
Page 32
Figure 19: Consecutive WRITE-to-WRITE COMMAND ADDRESS t DQSS (NOM) Notes uninterrupted burst shown. 3. Each WRITE command may be to any bank. Figure 20: Nonconsecutive WRITE-to-WRITE COMMAND ADDRESS t DQSS (NOM) Notes: ...
Page 33
Figure 21: Random WRITE Cycles CK# COMMAND ADDRESS DQS DM Notes ( the next data-in following D burst order. 3. Programmed cases shown. ...
Page 34
Figure 22: WRITE-to-READ – Uninterrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS DQSS (MAX) DQS DQ DM Notes: ...
Page 35
Figure 23: WRITE-to-READ – Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM Notes: ...
Page 36
Figure 24: WRITE-to-READ – Odd Number of Data, Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS ...
Page 37
Figure 25: WRITE-to-PRECHARGE – Uninterrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM Notes: ...
Page 38
Figure 26: WRITE-to-PRECHARGE – Interrupting T0 CK# CK COMMAND WRITE Bank a , ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM ...
Page 39
Figure 27: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting T0 CK# CK COMMAND WRITE Bank a, ADDRESS Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS ...
Page 40
PRECHARGE The PRECHARGE command (Figure 28) is used to deactivate the open row in a partic- ular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time ( determines ...
Page 41
Power-Down Power-down is entered when CKE is registered LOW. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is ...
Page 42
Truth Tables Table 8: Truth Table – CKE Notes: 1–5 CKE CKE Current State n (Active) Power-Down L L (Precharge) Power-Down L L Self refresh L H (Active) Power-Down L H (Precharge) Power-Down L H Self refresh ...
Page 43
Table 9: Truth Table – Current State Bank n - Command to Bank n Notes: 1–6; notes appear below and on next page Current State CS# RAS# Any Idle Row ...
Page 44
The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. 6. All states and sequences not shown are illegal or reserved. 7. Not ...
Page 45
Table 10: Truth Table – Current State Bank n - Command to Bank m Notes: 1–6; notes appear below and on next page Current State CS# RAS# Any Idle X X Row L L activating, L ...
Page 46
The access period starts with registration of the command and ends where the precharge period (or precharge enabled or a write with auto precharge is enabled any command to other banks ...
Page 47
Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of ...
Page 48
Table 13: Capacitance Notes: 13; notes appear on pages 52–54 Parameter Delta input/output capacitance: DQs, DQS, DM Delta input capacitance: Command and address Delta input capacitance: CK, CK# Input/output capacitance: DQs, DQS, DM Input capacitance: Address Input capacitance: Command Input ...
Page 49
Table 14: I Specifications and Conditions (continued) DD Notes: 1–5, 7, 10, 12, 14 notes appear on pages 52–54; V Parameter/Condition Auto refresh: Burst refresh; CKE = HIGH; Address and control inputs are switching; Data bus inputs are stable Precharge ...
Page 50
Table 15: Electrical Characteristics and Recommended AC Operating Conditions Notes: 1–6, 27; notes appear on pages 52–54 Characteristics Parameter Access window of DQs from CK/CK# Clock cycle time CK high-level width CK low-level width t Minimum CKE HIGH/LOW ...
Page 51
Table 15: Electrical Characteristics and Recommended AC Operating Conditions (continued) Notes: 1–6, 27; notes appear on pages 52–54 Characteristics Parameter DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS ...
Page 52
Notes 1. All voltages referenced to Vss. 2. All parameters assume proper device initialization. 3. Tests for AC timing nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. ...
Page 53
The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 17. This is not a device limit. The device ...
Page 54
Values for I values are estimated. 37. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and addresses) are measured between 38. DAL = ( next higher integer. 39. These ...
Page 55
Timing Diagrams Figure 31: x16 Data Output Timing – CK# CK LDQS DQ (Last data valid (First data no longer valid) DQ (Last data valid) DQ (First data no longer valid) DQ0 - ...
Page 56
Figure 32: Data Output Timing – T0 CK# CK COMMAND READ 1 DQS, or LDQS/UDQS 2 All DQ values, collectively Notes transitioning after DQS transition define 2. All DQ must transition the DQ ...
Page 57
Figure 34: Initialize and Load Mode Registers ( ( ) ) CK LVCMOS HIGH LEVEL ( ( ) ) CKE ( ( ...
Page 58
Figure 35: Power-Down Mode (Active or Precharge CKE ALID 1 COMMAND ADDR V ALI D DQS DQ DM Powe r -Dow n ...
Page 59
Figure 36: Auto Refresh Mode CKE NOP 2 COMMAND PRE 1 A0–A9, A11 ALL BANKS 1 A10 ONE BANK Bank(s) 4 ...
Page 60
Figure 37: Self Refresh Mode T0 CK CKE COMMAND NOP ADDR DQS Notes: 1. Clock must be stable before exiting self refresh ...
Page 61
Figure 38: Bank Read – Without Auto Precharge CKE COMMAND 6 ACT NOP A0– A11 A10 ...
Page 62
Figure 39: Bank Read – with Auto Precharge CKE COMMAND ACT NOP A0– A11 A10 ...
Page 63
Figure 40: Bank Write – Without Auto Precharge CKE NOP 6 COMMAND ACT A0- A11 A10 ...
Page 64
Figure 41: Bank Write – with Auto Precharge CKE NOP 5 COMMAND ACT A0- A11 A10 ...
Page 65
Figure 42: Write – DM Operation CKE NOP 6 COMMAND ACT A0–A9 A11 RA A10 ...
Page 66
Package Dimensions Figure 43: 60-Ball VFBGA Package SEATING PLANE C 0.10 C 60X Ø 0.45 6.40 SOLDER BALL DIAMETER REFERS 0.80 TYP TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS Ø 0.42 BALL A9 7.20 3.60 3.20 8.00 ±0.10 ...