MT46H8M16LFCF-10 IT TR Micron Technology Inc, MT46H8M16LFCF-10 IT TR Datasheet - Page 50

IC DDR SDRAM 128MBIT 60VFBGA

MT46H8M16LFCF-10 IT TR

Manufacturer Part Number
MT46H8M16LFCF-10 IT TR
Description
IC DDR SDRAM 128MBIT 60VFBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT46H8M16LFCF-10 IT TR

Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
128M (8Mx16)
Speed
100MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
-40°C ~ 85°C
Package / Case
60-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 15:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
AC Characteristics
Parameter
Access window of DQs from CK/CK#
Clock cycle time
CK high-level width
CK low-level width
Minimum
Auto precharge write recovery + precharge time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high-pulse width
DQS input low-pulse width
DQS–DQ skew, DQS to last DQ valid, per group,
per access
WRITE command to first DQS latching transition
DQS falling edge from CK rising – hold time
DQS falling edge to CK rising – setup time
Data valid output window (DVW)
Half-clock period
Data-out High-Z window from CK/CK#
Data-out Low-Z window from CK/CK#
Address and control input hold time
(fast slew rate)
Address and control input hold time
(slow slew rate)
Address and control input setup time
(fast slew rate)
Address and control input setup time
(slow slew rate)
Address and control input pulse width
LOAD MODE REGISTER command cycle time
DQ–DQS hold, DQS to first DQ to go non-valid,
per access
Data hold skew factor
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE/AUTO REFRESH command
period
ACTIVE-to-READ or WRITE delay
Average periodic refresh interval
AUTO REFRESH command period
PRECHARGE command period
t
CKE HIGH/LOW time
Electrical Characteristics and Recommended AC Operating Conditions
Notes: 1–6, 27; notes appear on pages 52–54; V
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
Symbol
t
t
t
DQSCK
t
t
t
t
t
t
t
t
t
t
DQSH
DQSQ
AC(3)
AC(2)
DIPW
t
t
t
t
CK(3)
CK(2)
t
t
DQSL
DQSS
HZ(3)
HZ(2)
t
t
t
t
MRD
t
t
t
DAL
DSH
t
t
QHS
RCD
REFI
CKE
t
t
t
t
IPW
RAS
t
t
t
DSS
t
RFC
DH
na
IH
IH
QH
CH
HP
DS
IS
IS
RC
RP
CL
LZ
F
S
F
S
50
DD
t
CH,
Q = +1.8V ±0.1V, V
-
Min
0.45
0.45
0.75
0.75
0.75
t
22.5
97.5
22.5
t
2.5
2.0
7.5
2.5
0.4
0.4
0.2
0.2
1.0
1.3
1.5
1.3
1.5
3.0
QHS
12
t
45
75
HP
2
2
QH -
t
t
DS +
128Mb: 8 Meg x 16 Mobile DDR SDRAM
CL
-75
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSQ
t
DH
70,000
Max
0.55
0.55
1.25
0.75
15.6
6.0
6.5
6.0
0.6
0.6
0.6
6.0
6.5
DD
t
CH,
-
Min
0.45
0.45
0.75
t
t
2.0
2.0
9.6
1.1
1.1
2.5
0.4
0.4
0.2
0.2
1.0
1.5
1.7
1.5
1.7
3.4
QHS
= +1.8V ±0.1V
15
t
50
80
30
80
30
HP
2
2
QH -
t
t
DS +
CL
Electrical Specifications
-10
t
DQSQ
t
DH
70,000
Max
0.55
0.55
1.25
15.6
7.0
7.0
7.0
0.6
0.6
0.7
7.0
7.0
©2004 Micron Technology, Inc. All rights reserved.
1
Units
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
ns
ns
CK
CK
CK
CK
CK
ns
ns
ns
ns
CK
ns
µs
23, 28, 37
23, 28, 37
Notes
22, 23
15, 33
14, 37
14, 37
14, 37
14, 37
22, 23
38
39
22
29
15
39
30
20
35
7
7

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