MT46H8M16LFCF-10 IT TR Micron Technology Inc, MT46H8M16LFCF-10 IT TR Datasheet - Page 17

• Manufacturer Part Number: MT46H8M16LFCF-10 IT TR
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M16LFCF-10 IT TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Auto Precharge
BURST TERMINATE
AUTO REFRESH
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
concurrent auto precharge, where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer in the current bank and does
not violate any other timing parameters. Input A10 determines whether one or all banks
are to be precharged, and in the case where only one bank is to be precharged, inputs
BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank
has been precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued to that bank. A PRECHARGE command will be treated
as a NOP if there is no open row in that bank (idle state), or if the previously open row is
already in the process of precharging.
Auto precharge is a feature which performs the same individual-bank precharge func-
tion described above, but without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
Auto precharge is nonpersistent in that it is either enabled or disabled for each indi-
vidual READ or WRITE command. This device supports concurrent auto precharge if the
command to the other bank does not interrupt the data transfer to the current bank.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. This “earliest valid stage” is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, without violating
each burst type in “Operations” on page 19. The user must not issue another command
to the same bank until the precharge time (
The BURST TERMINATE command is used to truncate READ bursts (with auto
precharge disabled). The most recently registered READ command prior to the BURST
TERMINATE command will be truncated, as shown in “Operations” on page 19. The
open page which the READ burst was terminated from remains open.
AUTO REFRESH is used during normal operation of the Mobile DDR SDRAM and is
analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAMs. This
command is nonpersistent, so it must be issued each time a refresh is required.
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command. The 128Mb Mobile DDR
SDRAM requires AUTO REFRESH cycles at an average interval of 15.625µs (maximum).
To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided.
Although not a JEDEC requirement, to provide for future functionality features, CKE
must be active (HIGH) during the auto refresh period. The auto refresh period begins
when the AUTO REFRESH command is registered and ends
17
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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RAS (MIN), as described for
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©2004 Micron Technology, Inc. All rights reserved.
Commands