MT46H8M16LFCF-10 IT TR Micron Technology Inc, MT46H8M16LFCF-10 IT TR Datasheet - Page 29

• Manufacturer Part Number: MT46H8M16LFCF-10 IT TR
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M16LFCF-10 IT TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WRITEs
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
WRITE bursts are initiated with a WRITE command, as shown in Figure 17 on page 30.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the WRITE
commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first corresponding rising edge of DQS
(
clock cycle). All of the WRITE diagrams show the nominal case, and where the two
extreme cases (i.e.,
been included. Figure 18 on page 31 shows the nominal case and the extremes of
for a burst of 4. Upon completion of a burst, assuming no other commands have been
initiated, the DQs will remain High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with or truncated with a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied after
either the last element of a completed burst or the last desired data element of a longer
burst which is being truncated. The new WRITE command should be issued x cycles
after the first WRITE command, where x equals the number of desired data element
pairs (pairs are required by the 2n-prefetch architecture).
Figure 19 on page 32 shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 20 on page 32. Full-speed random write accesses within a
page or pages can be performed, as shown in Figure 21 on page 33.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE without truncating the WRITE burst,
on page 34.
Data for any WRITE burst may be truncated by a subsequent READ command, as shown
in Figure 23 on page 35. Note that only the data-in pairs that are registered prior to the
t
masked with DM, as shown in Figure 24 on page 36.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst,
Figure 25 on page 37.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 26 on page 38 and Figure 27 on page 39. Note that only the data-in pairs
that are registered prior to the
subsequent data-in should be masked with DM, as shown in Figure 26 on page 38 and
Figure 27 on page 39. After the PRECHARGE command, a subsequent command to the
same bank cannot be issued until
WTR period are written to the internal array, and any subsequent data-in should be
t
DQSS) is specified with a relatively wide range (from 75 percent to 125 percent of one
t
DQSS [MIN] and
29
t
WR period are written to the internal array, and any
t
RP is met.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
t
DQSS [MAX]) might not be intuitive, they have also
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WTR should be met, as shown in Figure 22
t
WR should be met, as shown in
©2004 Micron Technology, Inc. All rights reserved.
Operations
t
DQSS