NAND01GW4B2AN6E STMicroelectronics, NAND01GW4B2AN6E Datasheet
NAND01GW4B2AN6E
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NAND01GW4B2AN6E Summary of contents
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... Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory Feature summary High Density NAND Flash memories – Gbit memory array – 64Mbit spare area – Cost effective solutions for mass storage applications NAND interface – x16 bus width – Multiplexed Address/ Data – ...
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Table 1. Product List NAND01G-B NAND02G-B 1. x16 organization only available for MCP Products. 2/64 (1) Reference NAND01G-B, NAND02G-B Part Number NAND01GR3B NAND01GW3B NAND01GR4B NAND01GW4B NAND02GR3B NAND02GW3B NAND02GR4B NAND02GW4B ...
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... NAND01G-B, NAND02G-B Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Inputs/Outputs (I/O0-I/O7 3.2 Inputs/Outputs (I/O8-I/O15 3.3 Address Latch Enable (AL 3.4 Command Latch Enable (CL 3.5 Chip Enable ( 3.6 Read Enable ( 3.7 Power-Up Read Enable, Lock/Unlock Enable (PRL ...
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Contents 6.1.2 6.2 Cache Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NAND01G-B, NAND02G-B 10 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Product List ...
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... Figure 3. TSOP48 Connections, x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4. FBGA63 Connections, x8 devices (Top view through package Figure 5. FBGA63 Connections, x16 devices (Top view through package Figure 6. Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7. Read Operations Figure 8. Random Data Output During Sequential Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9. Cache Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 10. ...
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... During Cache Programming, the device loads the data in a Cache Register while the previous data is transferred to the Page Buffer and programmed into the memory array. During Cache Reading, the device loads the data in a Cache Register while the previous data is transferred to the I/O Buffers to be read. ...
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... JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK trademark. For information on how to order these options refer to Scheme. Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to ’1’. See Table 2: Product Table 2 ...
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... MCP 10/64 P/E/R Controller, High Voltage Generator I/O8-I/O15, x16 E R I/O0-I/O7, x8/x16 W NAND Flash PRL V SS NAND01G-B, NAND02G-B NAND Flash Memory Array Page Buffer Cache Register Y Decoder I/O Buffers & Latches I/O0-I/O7, x8/x16 I/O8-I/O15, x16 RB AI09372b AI09373b ...
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NAND01G-B, NAND02G-B Table 3. Signal Names I/O8-15 I/O0 PRL Data Input/Outputs for x16 devices Data Input/Outputs, Address Inputs, or Command Inputs for x8 and x16 devices Address ...
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Summary description Figure 3. TSOP48 Connections, x8 devices 12/ NAND Flash (x8 ...
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NAND01G-B, NAND02G-B Figure 4. FBGA63 Connections, x8 devices (Top view through package ...
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Summary description Figure 5. FBGA63 Connections, x16 devices (Top view through package 14/ ...
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... Memory array organization The memory array is made up of NAND structures where 32 cells are connected in series. The memory array is organized in blocks where each block contains 64 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store Error correction Codes, software flags or Bad Block identification ...
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... Memory array organization Figure 6. Memory Array Organization x8 DEVICES Block = 64 Pages Page = 2112 Bytes (2,048 + 64) Main Area Block Page 2048 Bytes Page Buffer, 2112 Bytes 2,048 Bytes 16/64 Block Page 8 bits 64 Bytes 64 8 bits Bytes NAND01G-B, NAND02G-B x16 DEVICES Block = 64 Pages Page = 1056 Words (1024 + 32) ...
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... Interface. When CL is high, the inputs are latched on the rising edge of Write Enable. 3.5 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is low, V high while the device is busy, the device remains selected and does not go into standby IH mode ...
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... V Supply Voltage DD V provides the power supply to the internal core of the memory device the main DD power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever V Table 22 and Table program/erase during power-transitions ...
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... Address Input Address Input bus operations are used to input the memory addresses. Four bus cycles are required to input the addresses for 1Gb devices whereas five bus cycles are required for the 2Gb device (refer to The addresses are accepted when Chip Enable is Low, Address Latch Enable is High, Command Latch Enable is Low and Read Enable is High ...
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... Data Output Data Output bus operations are used to read: the data in the memory array, the Status Register, the lock status, the Electronic Signature and the Unique Identifier. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low ...
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NAND01G-B, NAND02G-B Table 7. Address Insertion, x16 Devices I/O8- Bus (1) Cycle I/O15 th( Any additional address input cycles will be ignored. 2. The fifth ...
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Command Set 5 Command Set All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal ...
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... Device operations The following section gives the details of the device operations. 6.1 Read Memory Array At Power-Up the device defaults to Read mode. To enter Read mode from another mode the Read command must be issued, see issued, subsequent consecutive Read commands only require the confirm command code (30h) ...
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Device operations Figure 7. Read Operations I/O Address Input 00h Command Code 1. Highest address depends on device density. 24/64 tBLBH1 30h Data Output (sequentially) Command Busy Code NAND01G-B, NAND02G-B ai08657b ...
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NAND01G-B, NAND02G-B Figure 8. Random Data Output During Sequential Data Output tBLBH1 (Read Busy time Address 30h I/O 00h Inputs Cmd Cmd Code Code 5 Add cycles Row Add 1,2,3 Col Add 1,2 Main Area Busy 05h Data ...
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Device operations 6.2 Cache Read The Cache Read operation is used to improve the read throughput by reading data using the Cache Register. As soon as the user starts to read one page, the device automatically loads the next page ...
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... NAND01G-B, NAND02G-B 6.3 Page Program The Page Program operation is the standard operation to program data to the memory array. Generally, data is programmed sequentially, however the device does support Random Input within a page. The memory array is programmed by page, however partial page programming is allowed where any number of Bytes (1 to 2112) or Words (1 to 1056) can be programmed. ...
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Device operations Figure 10. Page Program Operation RB I/O 80h Page Program Setup Code Figure 11. Random Data Input During Sequential Data Input RB Address I/O 80h Data Intput Inputs Cmd Code 5 Add cycles Row Add 1,2,3 Col Add ...
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... The Copy Back Program operation is used to copy the data stored in one page and reprogram it in another page. The Copy Back Program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block ...
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Device operations Figure 12. Copy Back Program Source I/O 00h Add Inputs Read Code (Read Busy time Copy back program is only permitted between odd address pages or even address pages. Figure 13. Page Copy Back Program with ...
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... Once the data is loaded into the Page Buffer the P/E/R Controller programs the data into the memory array. As soon as the Cache Registers are empty (after t Cache program command can be issued, while the internal programming is still executing. Once the program operation has started the Status Register can be read using the Read Status Register command. During Cache Program operations SR5 can be read to find out whether the internal programming is ongoing (SR5 = ‘ ...
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... The Reset command is used to reset the Command Interface and Status Register. If the Reset command is issued during any operation, the operation will be aborted was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. ...
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NAND01G-B, NAND02G-B 6.8 Read Status Register The device contains a Status Register which provides information on the current or previous Program or Erase operation. The various bits in the Status Register convey information and errors on the operation. The Status ...
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... The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The Error Bit is set to ’1’ when a program or erase operation has failed to write the correct data to the memory. If the Error Bit is set to ‘0’ the operation has completed successfully. The Error Bit SR0 Cache Program operation, indicates a failure on Page N. ...
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NAND01G-B, NAND02G-B 6.9 Read Electronic Signature The device contains a Manufacturer Code and Device Code. To read these codes three steps are required: 1. one Bus Write cycle to issue the Read Electronic Signature command (90h) 2. one Bus Write ...
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... It features a Write Protect, WP, pin, which can be used to protect the device against program and erase operations recommended to keep down. In addition, to protect the memory from any involuntary program/erase operations during power-transitions, the device has an internal voltage detector which disables all functions whenever V is below V ...
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NAND01G-B, NAND02G-B If the Start Block Address is the same as the End Block Address, only one block is unlocked. Only one consecutive area of blocks can be unlocked at any one time not possible to unlock multiple ...
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Data protection Figure 17. Read Block Lock Status Operation W R I/O 7Ah Read Block Lock Status Command 1. Three address cycles are required for 2 Gb devices. 1Gb devices only require two address cycles. Table 16. Block Lock Status ...
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NAND01G-B, NAND02G-B Figure 18. Block Protection State Diagram Block Unlock Command (start + end block address) Unlocked in Locked Area Blocks Lock-Down Command 1. PRL must be High for the software commands to be accepted. Power-Up Locked Blocks Lock-Down Blocks ...
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... Table 18 Wear-Leveling Algorithm and an Error Correction Code, to extend the number of program and erase cycles and increase the data retention. To help integrate a NAND memory into an application ST Microelectronics can provide a File System OS Native reference software, which supports the basic commands of file management. Contact the nearest ST Microelectronics sales office for more details. ...
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NAND01G-B, NAND02G-B Table 17. Block Failure Operation Erase Program Read Figure 19. Bad Block Management Flowchart Figure 20. Garbage Collection Valid Page Invalid Page Recommended Procedure Block Replacement Block Replacement or ECC START Block Address = Block 0 Increment Block ...
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... After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations it is recommended to implement a Garbage Collection algorithm Garbage Collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see Figure 20) ...
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NAND01G-B, NAND02G-B Figure 21. Error Detection 8.6 Hardware Simulation models 8.6.1 Behavioral simulation models Denali Software Corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior ...
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Program and Erase Times and Endurance cycles 9 Program and Erase Times and Endurance cycles The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 18. Table 18. Program, Erase Times and ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 19. ...
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DC And AC parameters 11 DC And AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from ...
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NAND01G-B, NAND02G-B Table 22. DC Characteristics, 1.8V Devices Symbol Parameter I DD1 Operating I Current DD2 I DD3 I Standby Current (CMOS) DD5 I Input Leakage Current LI I Output Leakage Current LO V Input High Voltage IH V Input ...
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DC And AC parameters Table 23. DC Characteristics, 3V Devices Symbol Parameter I DD1 Operating I Current DD2 I DD3 Standby current (TTL) I DD4 I Standby Current (CMOS) DD5 I Input Leakage Current LI I Output Leakage Current LO ...
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NAND01G-B, NAND02G-B Table 24. AC Characteristics for Command, Address, Data Input Alt. Symbol Symbol t Address Latch Low to Write Enable Low ALLWL t ALS t Address Latch High to Write Enable Low ALHWL Command Latch High to Write Enable ...
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DC And AC parameters Table 25. AC Characteristics for Operations Alt. Symbol Symbol t Address Latch Low to ALLRL1 t AR Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 t t ...
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NAND01G-B, NAND02G-B Figure 23. Command Latch AC Waveforms CL tCLHWL (CL Setup time) tELWL (E Setup time tALLWL (ALSetup time) AL I/O Figure 24. Address Latch AC Waveforms CL tELWL (E Setup time) E tWLWH W tALHWL (AL ...
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DC And AC parameters Figure 25. Data Input Latch AC Waveforms CL E tALLWL (ALSetup time) AL tWLWH W (Data Setup time) I/O 1. Data In Last is 2112 in x8 devices and 1056 in x16 devices. Figure 26. Sequential ...
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NAND01G-B, NAND02G-B Figure 27. Read Status Register AC Waveform CL tCLHWL E tELWL W R (Data Setup time) I/O Figure 28. Read Electronic Signature AC Waveform I/O 90h Read Electronic Signature Command 1. Refer to ...
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DC And AC parameters Figure 29. Page Read Operation AC Waveform CL E tWLWL Add.N Add.N I/O 00h cycle 1 cycle 2 Command Address N Input Code 1. A fifth address cycle is required for 2Gb ...
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NAND01G-B, NAND02G-B Figure 30. Page Program AC Waveform CL E tWLWL (Write Cycle time Add.N I/O 80h cycle 1 RB Page Program Setup Code 1. A fifth address cycle is required for 2Gb devices. tWLWL Add.N Add.N ...
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DC And AC parameters Figure 31. Block Erase AC Waveform CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Block Address Input Setup Command 1. Address cycle 3 is required for 2Gb ...
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NAND01G-B, NAND02G-B 11.1 Ready/Busy Signal electrical characteristics Figure 34, Figure 33 signal. The value required for the resistor R So, where I is the sum of the input currents of all the devices tied to the Ready/Busy signal ...
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DC And AC parameters Figure 35. Resistor Value Versus Waveform Timings For Ready/Busy Signal 1.8V 30pF 400 300 200 1.7 100 0. 1.7 1 ...
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NAND01G-B, NAND02G-B 12 Package mechanical Figure 37. TSOP48 - 48 lead Plastic Thin Small Outline mm, Package Outline DIE 1. Drawing is not to scale. Table 26. TSOP48 - 48 lead Plastic Thin Small ...
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Package mechanical Figure 38. VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Outline Drawing is not to scale Table 27. VFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data Symbol Typ A ...
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NAND01G-B, NAND02G-B Figure 39. TFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Outline Drawing is not to scale Table 28. TFBGA63 9.5x12mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data Symbol Typ A ...
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... E = Lead Free Package, Standard Packing F = Lead Free Package, Tape & Reel Packing Devices are shipped from the factory with the memory content bits, in valid blocks, erased to ’1’. For further information on any aspect of this device, please contact your nearest ST Sales Office. ...
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NAND01G-B, NAND02G-B 14 Revision history Table 30. Document Revision History Date Version 25-Feb-2005 16-Aug-2005 18-Oct-2005 13-Feb-2006 1 First Issue Automatic Page 0 Read feature removed throughout document. LFBGA63 package removed throughout document. Section 11.2: Data Protection Circuit for AC Characteristics ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...