NAND01GW4B2AN6E STMicroelectronics, NAND01GW4B2AN6E Datasheet - Page 26

• Manufacturer Part Number: NAND01GW4B2AN6E
• Description: IC FLASH 1GBIT 48TSOP
• Manufacturer: STMicroelectronics

Specifications of NAND01GW4B2AN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 1G (64M x 16)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

Device operations
6.2
Figure 9.
26/64
RB
I/O
Cache Read
The Cache Read operation is used to improve the read throughput by reading data using
the Cache Register. As soon as the user starts to read one page, the device automatically
loads the next page into the Cache Register.
An Cache Read operation consists of three steps (see
1.
2.
3.
The Start Address must be at the beginning of a page (Column Address = 00h, see
and
see
The Ready/Busy signal can be used to monitor the start of the operation. During the latency
period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if
the device is internally downloading page n+1.
Once the Cache Read operation has started, the Status Register can be read using the
Read Status Register command.
During the operation, SR5 can be read, to find out whether the internal reading is ongoing
(SR5 = ‘0’), or has completed (SR5 = ‘1’), while SR6 indicates whether the Cache Register
is ready to download new data.
To exit the Cache Read operation an Exit Cache Read command must be issued (see
Table
If the Exit Cache Read command is issued while the device is internally reading page n+1,
page n will still be output, but not page n+1.
Cache Read Operation
Setup
Read
Code
00h
Figure 9
Table
One bus cycle is required to setup the Cache Read command (the same as the
standard Read command)
Four or Five (refer to
Start Address
One bus cycle is required to issue the Cache Read confirm command to start the P/E/R
Controller.
10).
Address
9). This allows the data to be output uninterrupted after the latency time (t
Inputs
(Read Busy time)
tBLBH1
Confirm
Cache
Read
Code
31h
Table 6
Busy
and
1st page
Table
2nd page
7) bus cycles are then required to input the
Block N
3rd page
Table 10:
Data Output
NAND01G-B, NAND02G-B
last page
Commands):
Cache
Read
Code
Exit
34h
Table 8
BLBH1
ai08661
),