PCF85162T/1,118 NXP Semiconductors, PCF85162T/1,118 Datasheet - Page 6

• Manufacturer Part Number: PCF85162T/1,118
• Description: IC LCD DISPLAY DVR 32SEG 48TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCF85162T/1,118

• Package / Case: 48-TSSOP
• Display Type: LCD
• Configuration: 32 Segment
• Interface: I²C
• Digits Or Characters: Any Digit Type
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 16
• Number Of Segments: 128
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Attached Touch Screen: No
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Dc: 1123
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-5059-2

NXP Semiconductors
PCF85162_2
Product data sheet
7.1 Power-on reset
7.2 LCD bias generator
The host microprocessor or microcontroller maintains the 2-line I
channel with the PCF85162. The internal oscillator is enabled by connecting
pin OSC to pin V
are generated internally. The only other connections required to complete the system are
to the power supplies (V
At power-on the PCF85162 resets to the following starting conditions:
Remark: Do not transfer data on the I
the reset action to complete.
Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of
three impedances connected in series between V
bypassed by switch if the
configuration is selected. The LCD voltage can be temperature compensated externally,
using the supply to pin V
Fig 4.
•
•
•
•
•
•
•
All backplane and segment outputs are set to V
The selected drive mode is: 1:4 multiplex with
Blinking is switched off
Input and output bank selectors are reset
The I
The data pointer and the subaddress counter are cleared (set to logic 0)
Display is disabled
V
V
SS
DD
CONTROLLER
PROCESSOR/
2
The resistance of the power lines must be kept to a minimum.
Typical system configuration
C-bus interface is initialized
MICRO-
MICRO-
HOST
R ≤
All information provided in this document is subject to legal disclaimers.
SS
2C
. The appropriate biasing voltages for the multiplexed LCD waveforms
t
r
b
Rev. 02 — 7 May 2010
DD
LCD
1
, V
⁄
2
.
bias voltage level for the 1:2 multiplex drive mode
SS
, and V
SDA
SCL
OSC
10
11
15
2
16
C-bus for at least 1 ms after a power-on to allow
LCD
A0
14
17
) and the LCD panel chosen for the application.
Universal LCD driver for low multiplex rates
PCF85162
A1
V
DD
18
A2
21
V
19
LCD
LCD
1
SA0
⁄
LCD
3
20
bias
and V
V
SS
32 segment drives
4 backplanes
SS
. The center impedance is
2
C-bus communication
PCF85162
© NXP B.V. 2010. All rights reserved.
LCD PANEL
(up to 128
elements)
013aaa066
6 of 43