ISL6565ACBZ Intersil, ISL6565ACBZ Datasheet - Page 11

• Manufacturer Part Number: ISL6565ACBZ
• Description: IC CTRLR PWM MULTIPHASE 28-SOIC
• Manufacturer: Intersil

Specifications of ISL6565ACBZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.7%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figures 19 and 20 in the section entitled Input Capacitor
Selection can be used to determine the input-capacitor RMS
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution.
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the
ISL6565A, ISL6565B is three. One switching cycle is defined
as the time between PWM1 pulse termination signals. The
pulse termination signal is the internally generated clock
signal that triggers the falling edge of PWM1. The cycle time
of the pulse termination signal is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. Each cycle begins when the clock signal commands
PWM1 to go low. The PWM1 transition signals the channel-1
MOSFET driver to turn off the channel-1 upper MOSFET
and turn on the channel-1 synchronous MOSFET. In the
default channel configuration, the PWM2 pulse terminates
1/3 of a cycle after the PWM1 pulse. The PWM3 pulse
terminates 1/3 of a cycle after PWM2.
If PWM3 is connected to VCC, two channel operation is
selected and the PWM2 pulse terminates 1/2 of a cycle after
the PWM1 pulse terminates.
Once a PWM pulse transitions low, it is held low for a
minimum of 1/3 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
V
sawtooth ramp as illustrated in Figure 6. When the modified
V
transitions high. The MOSFET driver detects the change in
state of the PWM signal and turns off the synchronous
MOSFET and turns on the upper MOSFET. The PWM signal
will remain high until the pulse termination signal marks the
beginning of the next cycle by triggering the PWM signal low.
Current Sampling
During the forced off-time, following a PWM transition low,
the current-sense amplifier uses the ISEN inputs to
reproduce a signal proportional to the inductor current, I
No matter which current-sense method is employed, the
sense current (I
inductor current. The sample window opens exactly 1/6 of
the switching period, t
sample window then stays open for a fixed amount of time,
t
illustrated in Figure 3.
SAMPLE
t
SAMPLE
COMP
COMP
, minus the current correction signal relative to the
voltage crosses the sawtooth ramp, the PWM output
, and is equal to 1/6 of the switching period, t
=
t
--------- -
SW
6
SEN
=
----------------- -
6 f
) is simply a scaled version of the
⋅
SW
1
SW
, after the PWM transitions low. The
11
ISL6565A, ISL6565B
SW
(EQ. 3)
L
.
as
The sampled current, at the end of the t
proportional to the inductor current and is held until the next
switching period sample. The sampled current is used for
current balance, load-line regulation, and overcurrent
protection.
Current Sensing
The ISL6565A supports MOSFET r
while the ISL6565B supports inductor DCR current sensing.
The internal circuitry, shown in Figures 4 and 5, represent
channel n of an N-channel converter. This circuitry is
repeated for each channel in the converter, but may not be
active depending on the status of the PWM3 pin, as
described in the PWM Operation section.
MOSFET r
The ISL6565A senses the channel load current by sampling
the voltage across the lower MOSFET r
Figure 4. A ground-referenced operational amplifier, internal
to the ISL6565A, is connected to the PHASE node through a
resistor, R
the voltage drop across the r
while it is conducting. The resulting current into the ISEN pin
is proportional to the channel current, I
sampled and held as described in the Current Sampling
section. From Figure 4, the following equation for I
derived where I
I
n
=
I
L
r
----------------------
OLD SAMPLE
CURRENT
DS ON
R
ISEN
ISEN
DS(ON)
(
FIGURE 3. SAMPLE AND HOLD TIMING
)
. The voltage across R
L
is the channel current.
SENSING (ISL6565A ONLY)
PWM
SWITCHING PERIOD
DS(ON)
I
L
TIME
NEW SAMPLE CURRENT
t
SAMPLE
DS(ON)
of the lower MOSFET
ISEN
L
I
SEN
. The ISEN current is
DS(ON)
SAMPLE
is equivalent to
current sensing,
, as shown in
December 1, 2005
, is
n
is
FN9135.4
(EQ. 4)