ISL6565ACBZ Intersil, ISL6565ACBZ Datasheet - Page 18

• Manufacturer Part Number: ISL6565ACBZ
• Description: IC CTRLR PWM MULTIPHASE 28-SOIC
• Manufacturer: Intersil

Specifications of ISL6565ACBZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.7%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that transitions high when the converter is operating after
soft-start. PGOOD pulls low during shutdown and releases
high after a successful soft-start. PGOOD only transitions
low when an undervoltage condition is detected or the
controller is disabled by a reset from EN, ENLL, POR, or one
of the no-CPU VID codes. After an undervoltage event,
PGOOD will return high unless the controller has been
disabled. PGOOD does not automatically transition low upon
detection of an overvoltage condition.
Undervoltage Detection
The undervoltage threshold is set at 75% of the VID code.
When the output voltage at VSEN is below the undervoltage
threshold, PGOOD gets pulled low. No other action is taken
by the controller.
Overvoltage Protection
When VCC is above 1.4V, but otherwise not valid as defined
under Power on Reset in Electrical Specifications, the
overvoltage trip circuit is active using auxiliary circuitry. In
this state, an overvoltage trip occurs if the voltage at VSEN
exceeds 1.8V.
With valid VCC, the overvoltage circuit is sensitive to the
voltage at VDIFF. In this state, the trip level is 1.7V prior to
valid enable conditions being met as described in Enable
and Disable. The only exception to this is when the IC has
been disabled by an overvoltage trip. In that case the
overvoltage trip point is VID plus 200mV. During soft-start,
the overvoltage trip level is the higher of 1.7V or VID plus
200mV. Upon successful soft-start, the overvoltage trip level
is 200mV above VID. Two actions are taken by the
VDIFF
FIGURE 13. POWER GOOD AND PROTECTION CIRCUITRY
REFERENCE
DAC
75%
VID + 0.2V
UV
AND CONTROL LOGIC
SOFT-START, FAULT
+
-
OV
18
EACH CHANNEL
REPEAT FOR
OC
+
-
OC
+
-
110µA
I
1
ISL6565A, ISL6565B
PGOOD
OVP
110µA
I
AVG
ISL6565A, ISL6565B to protect the microprocessor load
when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low until the voltage at VSEN falls below
0.6V with valid VCC or 1.5V otherwise. This causes the
Intersil drivers to turn on the lower MOSFETs and pull the
output voltage below a level that might cause damage to the
load. The PWM outputs remain low until VDIFF falls to the
programmed DAC level at which time they enter a high-
impedance state. The Intersil drivers respond to the high-
impedance input by turning off both upper and lower
MOSFETs. If the overvoltage condition reoccurs, the
ISL6565A, ISL6565B will again command the lower
MOSFETs to turn on. The ISL6565A, ISL6565B will continue
to protect the load in this fashion as long as the overvoltage
condition recurs.
Simultaneous to the protective action of the PWM outputs, the
OVP pin pulls to VCC delivering up to 100mA to the gate of a
crowbar MOSFET or SCR placed either on the input rail or the
output rail. Turning on the MOSFET or SCR collapses the
power rail and causes a fuse placed further up stream to blow.
The fuse must be sized such that the MOSFET or SCR will
not overheat before the fuse blows. The OVP pin is tolerant to
12V (see Absolute Maximum Ratings), so an external resistor
pull up can be used to augment the driving capability. If using
a pull up resistor in conjunction with the internal overvoltage
protection function, care must be taken to avoid nuisance trips
that could occur when VCC is below 2V. In that case, the
controller is incapable of holding OVP low.
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6565A, ISL6565B is reset.
Cycling the voltage on EN, ENLL, or VCC below the POR-
falling threshold will reset the controller. Cycling the VID
codes will not reset the controller.
Overcurrent Protection
ISL6565A, ISL6565B has two levels of overcurrent
protection. Each phase is protected from a sustained
overcurrent condition on a delayed basis, while the
combined phase currents are protected on an instantaneous
basis.
In instantaneous protection mode, the ISL6565A, ISL6565B
takes advantage of the proportionality between the load
current and the average current, I
overcurrent condition. See the Channel-Current Balance
section for more detail on how the average current is
measured. The average current is continually compared with
a constant 110µA reference current as shown in Figure 6.
Once the average current exceeds the reference current, a
comparator triggers the converter to shutdown.
In individual overcurrent protection mode, the ISL6565A,
ISL6565B continuously compares the current of each channel
with the same 110µA reference current. If any channel current
exceeds the reference current continuously for eight
AVG
, to detect an
December 1, 2005
FN9135.4