ISL6565ACBZ Intersil, ISL6565ACBZ Datasheet - Page 19

• Manufacturer Part Number: ISL6565ACBZ
• Description: IC CTRLR PWM MULTIPHASE 28-SOIC
• Manufacturer: Intersil

Specifications of ISL6565ACBZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.7%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

consecutive cycles, the comparator triggers the converter to
shutdown.
At the beginning of overcurrent shutdown, the controller
places all PWM signals in a high-impedance state
commanding the Intersil MOSFET driver ICs to turn off both
upper and lower MOSFETs. The system remains in this state
for a period of 4096 switching cycles. If the controller is still
enabled at the end of this wait period, it will attempt a soft-
start (as shown in Figure 14). If the fault remains, the trip-
retry cycles will continue indefinitely until either the controller
is disabled or the fault is cleared. Note that the energy
delivered during trip-retry cycling is much less than during
full-load operation, so there is no thermal hazard.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and example
board layouts for all common microprocessor applications.
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board, whether through-hole components are permitted, the
total board space available for power-supply circuitry, and
the maximum amount of load current. Generally speaking,
the most economical solutions are those in which each
phase handles between 25A and 30A. All surface-mount
designs will tend toward the lower end of this current range.
FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE
0A
0V
OUTPUT CURRENT, 50A/DIV
OUTPUT VOLTAGE,
500mV/DIV
F
SW
= 500kHz
2ms/DIV
19
ISL6565A, ISL6565B
If through-hole MOSFETs and inductors can be used, higher
per-phase currents are possible. In cases where board
space is the limiting constraint, current can be pushed as
high as 40A per phase, but these designs require heat sinks
and forced air to cool the MOSFETs, inductors and heat-
dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is
simple, since virtually all of the loss in the lower MOSFET is
due to current conducted through the channel resistance
(r
output current, I
Equation 1), and d is the duty cycle (V
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I
frequency, f
the beginning and the end of the lower-MOSFET conduction
interval respectively.
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P
UPPER MOSFET POWER CALCULATION
In addition to r
MOSFET losses are due to currents conducted across the
input voltage (V
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode reverse-
recovery charge, Q
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 22,
P
P
DS(ON)
LOW 1
LOW 2
,
,
). In Equation 20, I
=
=
r
V
S
DS ON
D ON
, and the length of dead times, t
(
DS(ON)
(
IN
PP
)
) during switching. Since a substantially
)
f
S
is the peak-to-peak inductor current (see
rr



, and the upper MOSFET r
I
----- -
N
M


losses, a large portion of the upper-
I
----- -



N
M
2
(
+
M
1 d
I
-------- -
, V
M
–
PP
2
is the maximum continuous
D(ON)
 t

)
+
d1
I
--------------------------------
L PP
,
+
2
, the switching



12
I
----- -
OUT
(
N
M
1 d
LOW,1
–
–
I
-------- -
/V
PP
2
)
IN
d1



and P
).
t
DS(ON)
d2
and t
December 1, 2005
LOW,2
d2
(EQ. 20)
(EQ. 21)
FN9135.4
, at
.