ISL6565ACBZ Intersil, ISL6565ACBZ Datasheet - Page 15

• Manufacturer Part Number: ISL6565ACBZ
• Description: IC CTRLR PWM MULTIPHASE 28-SOIC
• Manufacturer: Intersil

Specifications of ISL6565ACBZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.7%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

As shown in Figure 7, a current proportional to the average
current in all active channels, I
load-line regulation resistor, R
across R
creating an output voltage droop with a steady-state value
defined as:
In most cases, each channel uses the same component
values to sense current. If this is the case you can derive a
more complete equation for V
method being used.
Output-Voltage Offset Programming
The ISL6565A, ISL6565B allows the designer to accurately
adjust the offset voltage by connecting a resistor, R
from the OFS pin to VCC or GND. When R
between OFS and VCC, the voltage across it is regulated to
2.0V. This causes a proportional current (I
the OFS pin and out of the FB pin. If R
ground, the voltage across it is regulated to 0.5V, and I
flows into the FB pin and out of the OFS pin. The offset
current flowing through the resistor between VDIFF and FB
will generate the desired offset voltage which is equal to the
product (I
8 and 9.
Once the desired output offset voltage has been determined,
use the following formulas to set R
For Positive Offset (connect R
For Negative Offset (connect R
V
V
V
R
R
DROOP
DROOP
DROOP
OFS
OFS
=
=
FB
--------------------------
V
--------------------------
V
0.5 R
OFS
=
=
=
2
OFFSET
OFFSET
×
I
I
------------ -
I
------------ - K
is proportional to the output current, effectively
AVG
×
OUT
OUT
R
N
N
x R
FB
FB
R
⋅
r
---------------------- R
FB
DS ON
R
FB
ISEN
⋅
). These functions are shown in Figures
(
----------------- - R
R
DCR
ISEN
)
FB
FB
15
DROOP
FB
OFS
AVG
OFS
. The resulting voltage drop
, flows from FB through a
OFS
to GND):
r
(ISL6565A ONLY)
DCR SENSING
(ISL6565B ONLY)
to VCC):
DS(ON)
for each current sense
OFS
:
OFS
OFS
SENSING
is connected to
) to flow into
is connected
ISL6565A, ISL6565B
OFS
(EQ. 10)
(EQ. 11)
(EQ. 12)
(EQ. 13)
(EQ. 14)
OFS
,
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs. The core-voltage regulator is required to monitor the
DAC inputs and respond to on-the-fly VID changes in a
controlled manner supervising a safe output voltage transition
without discontinuity or disruption.
V
R
V
R
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
OFS
OFS
OFS
OFS
+
-
+
-
VDIFF
VDIFF
VCC
I
OFS
GND
R
R
I
OFS
FB
FB
OFS
OFS
FB
FB
PROGRAMMING
PROGRAMMING
ISL6565A, ISL6565B
ISL6565A, ISL6565B
VREF
VREF
E/A
GND
E/A
GND
+
+
-
-
0.5V
0.5V
December 1, 2005
VCC
VCC
FN9135.4
+
+
-
-
2.0V
2.0V