ISL6565ACBZ Intersil, ISL6565ACBZ Datasheet - Page 17

• Manufacturer Part Number: ISL6565ACBZ
• Description: IC CTRLR PWM MULTIPHASE 28-SOIC
• Manufacturer: Intersil

Specifications of ISL6565ACBZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.7%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When each of these conditions is true, the controller
immediately begins the soft-start sequence.
Soft-Start
During soft-start, the DAC voltage ramps linearly from zero
to the programmed VID level. The PWM signals remain in
the high-impedance state until the controller detects that the
ramping DAC level has reached the output-voltage level.
This protects the system against the large, negative inductor
currents that would otherwise occur when starting with a pre-
2. The voltage on EN must be above 1.31V. The EN input
3. The voltage on ENLL must be logic high to enable the
4. The VID code must not be 111111 or 111110. These codes
ISL6565A, ISL6565B INTERNAL CIRCUIT
FIGURE 11. POWER SEQUENCING USING THRESHOLD-
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6565A, ISL6565B in shutdown until the
voltage at EN rises above 1.31V. The enable comparator
has about 100mV of hysteresis to prevent bounce. It is
important that the driver ICs reach their POR level before
the ISL6565A, ISL6565B becomes enabled. The
schematic in Figure 11 demonstrates sequencing the
ISL6565A, ISL6565B with the HIP660X family of Intersil
MOSFET drivers, which require 12V bias.
controller. This pin is typically connected to the
VID_PGOOD.
signal the controller that no load is present. The controller
will enter shut-down mode after receiving either of these
codes and will execute soft-start upon receiving any other
code. These codes can be used to enable or disable the
controller but it is not recommended. After receiving one
of these codes, the controller executes a 2-cycle delay
before changing the overvoltage trip level to the shut-
down level and disabling PWM. Overvoltage shutdown
cannot be reset using one of these codes.
CIRCUIT
FAULT LOGIC
SOFT-START
POR
AND
SENSITIVE ENABLE (EN) FUNCTION
ENABLE
COMPARATOR
17
+
-
1.24V
EXTERNAL CIRCUIT
VCC
EN
ENLL
10.7kΩ
1.40kΩ
+12V
ISL6565A, ISL6565B
existing charge on the output as the controller attempted to
regulate to 0V at the beginning of the soft-start cycle. The
soft-start time, t
switching cycles followed by a linear ramp with a rate
determined by the switching period, 1/f
For example, a regulator with a 250kHz switching frequency,
having VID set to 1.35V, has t
A 100mV offset exists on the remote-sense amplifier at the
beginning of soft-start and ramps to zero during the first 640
cycles of soft-start (704 cycles following enable). This
prevents the large inrush current that would otherwise occur
should the output voltage start out with a slight negative
bias.
During the first 640 cycles of soft-start (704 cycles following
enable) the DAC voltage increments the reference in 25mV
steps. The remainder of soft-start sees the DAC ramping
with 12.5mV steps.
Fault Monitoring and Protection
The ISL6565A, ISL6565B actively monitors output voltage
and current to detect fault conditions. Fault monitors trigger
protective measures to prevent damage to a microprocessor
load. One common power good indicator is provided for
linking to external system monitors. The schematic in
Figure 13 outlines the interaction between the fault monitors
and the power good signal.
t
SS
FIGURE 12. SOFT-START WAVEFORMS WITH AN UN-BIASED
=
64
-----------------------------------------
+
1280 VID
f
SW
OUTPUT. FSW = 500kHz
SS
⋅
, begins with a delay period equal to 64
2ms/DIV
VOUT, 500mV/DIV
500ms/DIV
SS
equal to 6.912ms.
SW
EN, 5V/DIV
.
December 1, 2005
(EQ. 19)
FN9135.4