ISL6565ACBZ Intersil, ISL6565ACBZ Datasheet - Page 23

• Manufacturer Part Number: ISL6565ACBZ
• Description: IC CTRLR PWM MULTIPHASE 28-SOIC
• Manufacturer: Intersil

Specifications of ISL6565ACBZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.7%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage-mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
Select a target bandwidth for the compensated system, f
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
Case 2:
Case 1:
FIGURE 17. COMPENSATION CONFIGURATION FOR
R
FB
LOAD-LINE REGULATED ISL6565A, ISL6565B
CIRCUIT
-------------------
2π LC
R
C
C
C
-------------------
2π LC
R
C
+
V
-
1
R
DROOP
C
C
=
=
C
1
=
=
R
------------------------------------------------------------ -
(
2π
C
≤
FB
2
R
----------------------------------- -
2πV
f
)
C
>
0
(OPTIONAL)
FB
V
--------------------------------------------
2
C
0.75V
<
f
PP
f
0
23
PP
2πf
----------------------------------- -
0
0.75V
----------------------------- -
2πC ESR
2
0.75 V
(
V
0.75V
R
2π
0
PP
IN
FB
V
(
COMP
1
VDIFF
)
pp
IN
2
R
f
0
IN
f
FB
FB
IN
0
2
LC
)
LC
LC
ISL6565A, ISL6565B
(EQ. 40)
0
.
0
.
Case 3:
In Equation 40, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V
peak sawtooth signal amplitude as described in Figure 6 and
Electrical Specifications.
Once selected, the compensation values in Equation 40
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R
value of R
oscilloscope until no further improvement is noted. Normally,
C
Equation 40 unless some performance issue is noted.
The optional capacitor C
noise away from the PWM comparator (see Figure 17). Keep
a position available for C
frequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ∆I,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, ∆V
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
C
will not need adjustment. Keep the value of C
C
while observing the transient performance on an
f
R
C
0
C
C
>
----------------------------- -
2πC ESR
=
=
R
0.75V
------------------------------------------------ -
2
2πV
2
FB
(
, is sometimes needed to bypass
, and be prepared to install a high-
1
----------------------------------------- -
0.75 V
PP
IN
2π f
)
R
(
ESR
FB
0
IN
V
f
0
(
pp
) C
ESR
C
L
L
. Slowly increase the
PP
)
is the peak-to-
December 1, 2005
C
MAX
from
FN9135.4
.