ISL6569ACR Intersil, ISL6569ACR Datasheet - Page 12

• Manufacturer Part Number: ISL6569ACR
• Description: IC CTRLR PWM BUCK 2PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6569ACR

• Pwm Type: Voltage/Current Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 2MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LOAD-LINE REGULATION
Microprocessor load current demands change from near no-
load to full load often during operation. The resulting sizable
transient current slew rate causes an output voltage spike
since the converter is not able to respond fast enough to the
rapidly changing current demands. The magnitude of the
spike is dictated by the ESR and ESL of the output
capacitors selected. In order to drive the cost of the output
capacitor solution down, one commonly accepted approach
is active voltage positioning. By adding a well controlled
output impedance, the output voltage can effectively be level
shifted in a direction which works against the voltage spike.
The average current of all the active channels, I
IOUT, see Figure 6. IOUT is connected to FB through a load-
line regulation resistor, R
R
an output voltage droop with a steady-state value defined as
In most cases, each channel uses the same R
sense current. A more complete expression for V
derived by combining Equations 4 and 5.
Droop is an optional feature of the ISL6569A. If active voltage
positioning is not required, simply leave the IOUT pin open.
REFERENCE OFFSET
Typical microprocessor tolerance windows are centered
around a nominal DAC set point. Implementing a load-line
requires offsetting the output voltage above this nominal
DAC set point; centering the load-line within the static
specification window. The ISL6569A features an internal
100µA current source which feeds out the OFS pin. Placing
a resistor from OFS and ground allows the user to set the
amount of positive offset desired directly to the reference
voltage. The voltage developed across the OFS resistor,
R
counters the DAC voltage at the error amplifier non-inverting
input. Select the resistor value based on the voltage offset
desired, V
V
V
R
FB
OFS
DROOP
DROOP
OFS
TABLE 1. VOLTAGE IDENTIFICATION CODES (Continued)
VID4
is proportional to the output current, effectively creating
1
1
1
1
1
1
, is divided down internally by a factor of 10 and directly
=
V
-------------------------- -
=
=
OFS
OFS
100µA
I
I
-------------
AVG
OUT
VID3
2
, using Equation 7
⋅
1
1
1
1
1
1
10
R
r
---------------------- R
DS ON
R
FB
ISEN
(
VID2
FB
0
0
1
1
1
1
)
. The resulting voltage drop across
FB
12
VID1
1
1
0
0
1
1
VID0
0
1
0
1
0
1
ISEN
AVG
DROOP
Shutdown
, flows out
value to
0.900
0.875
0.850
0.825
0.800
DAC
(EQ. 5)
(EQ. 6)
(EQ. 7)
is
ISL6569A
DYNAMIC VID
Next generation microprocessors can change VID inputs at
any time while the regulator is in operation. The power
management solution is required to monitor the DAC inputs
and respond to VID voltage transitions, or ‘on-the-fly’ VID
changes, in a controlled manner. Supervising the safe output
voltage transition within the DAC range of the processor
without discontinuity or disruption.
The ISL6569A checks the five VID inputs at the beginning of
each channel-1 switching cycle. If the VID code has
changed, the controller waits one complete switching cycle
to validate the new code. If the VID code is stable for this
entire switching cycle, then the controller will begin executing
the output voltage change. The controller begins
incrementing the reference voltage by making 25mV steps
every two switching cycles until it reaches the new VID code.
The total time required for a VID change, t
on the switching frequency (f
(∆VID), and the time before the next switching cycle begins.
Since the ISL6569A recognizes VID-code changes only at
the beginning of switching cycles, up to one full cycle may
pass before a VID change registers. This is followed by a
one-cycle wait before the output voltage begins to change.
The one-cycle uncertainty in Equation 8 is due to the
possibility that the VID code change may occur up to one full
cycle before being recognized.
The time required for a converter running with f
make a 1.2V to 1.4V reference-voltage change is between
30µs and 32µs as calculated using Equation 8. This example
is also illustrated in Figure 7.
---- - 2 VID
f
1.2V
1.2V
1
S


FIGURE 7. DYNAMIC-VID WAVEFORMS FOR 500kHz ISL6569A
----------------- - 1
0.025
∆
V
V
01110
REF
OUT
–
, 100mV/DIV
, 100mV/DIV


BASED MULTI-PHASE BUCK CONVERTER
<
t
DV
≤
00110
---- - 2 VID
f
1
S


----------------- -
0.025
VID CHANGE OCCURS
ANYWHERE HERE
∆
VID, 5V/DIV
S
5µs/DIV
), the size of the change


DV
, is dependent
S
December 29, 2004
= 500kHz to
FN9092.2
(EQ. 8)