ISL6569ACR Intersil, ISL6569ACR Datasheet - Page 13

• Manufacturer Part Number: ISL6569ACR
• Description: IC CTRLR PWM BUCK 2PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6569ACR

• Pwm Type: Voltage/Current Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 2MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Operation Initialization
Before converter operation is initialized, proper conditions
must exist on the enable and disable inputs. Once these
conditions are met, the controller begins a soft-start interval.
Once the output voltage is within the proper window of
operation, the PGOOD output changes state to update an
external system monitor.
Enable and Disable
The PWM outputs are held in a high-impedance state to
assure the drivers remain off while in shutdown mode. Four
separate input conditions must be met before the ISL6569A
is released from shutdown mode.
First, the bias voltage applied at VCC must reach the internal
power-on reset (POR) circuit rising threshold. Once this
threshold is met, the EN input signal becomes the gate for
soft-start initialization. Hysteresis between the rising and
falling thresholds insures that once enabled, the ISL6569A
will not inadvertently turn off unless the bias voltage drops
substantially. See Electrical Specifications for specifics on
POR rising and falling thresholds.
Second, the ISL6569A features an enable input (EN) for
power sequencing between the controller bias voltage and
another voltage rail. The enable comparator holds the
ISL6569A in shutdown until the voltage at EN rises above
1.23V. The enable comparator has about 90mV of hysteresis
to prevent bounce. It is important that the driver ICs reach
their POR level before the ISL6569A becomes enabled. The
schematic in Figure 8 demonstrates sequencing the
ISL6569A with the HIP660X family of Intersil MOSFET
drivers which require 12V bias.
Third, the frequency select/disable input (FS/DIS) will
shutdown the converter when pulled to ground. Under this
condition, the internal oscillator is disabled. The oscillator
resumes operation upon release of FS/DIS and a soft-start
sequence is initiated.
FIGURE 8. POWER SEQUENCING USING THRESHOLD-
OV LATCH
CIRCUIT
SIGNAL
ISL6569A INTERNAL CIRCUIT
POR
SENSITIVE ENABLE (EN) FUNCTION
ENABLE
COMPARATOR
1.23V (± 2%)
13
+
-
EXTERNAL CIRCUIT
VCC
EN
+5V
10.7kΩ
1.40kΩ
+12V
ISL6569A
Finally, the 11111 VID code is reserved as a signal to the
controller that no load is present. The controller will enter
shutdown mode after receiving this code and will start up
upon receiving any other code.
To enable the controller, VCC must be greater than the POR
threshold; the voltage on EN must be greater than 1.23V;
FS/DIS must not be grounded; and VID cannot be equal to
11111. Once these conditions are true, the controller
immediately initiates a soft-start sequence.
Soft-Start
The soft-start time, t
that increments with every pulse of the phase clock. For
example, a converter switching at 250kHz per phase has a
soft-start time of
During the soft-start interval, the soft-start voltage, V
increases linearly from zero to 140% of the programmed
DAC voltage. At the same time a current source, I
decreasing from 160µA down to zero. These signals are
connected as shown in Figure 9 (I
connected to FB depending on the particular application).
The ideal diodes in Figure 9 assure that the controller tries to
regulate its output to the lower of either the reference voltage
or V
(R
V
delay after the ISL6569A enables before the output voltage
starts moving. For example, if VID = 1.5V, R
= 8.3ms, the delay time can be expressed using Equation 10.
T
t
R
DELAY
RAMP
SS
FB
FB
FIGURE 9. RAMP CURRENT AND VOLTAGE FOR
RAMP
=
x 160µA), the first PWM pulse will not be seen until
EXTERNAL CIRCUIT
2048
------------ -
f
is greater than the R
=
SW
R
. Since I
C
-------------------------------------------------- -
1
+
=
REGULATING SOFT-START SLOPE
AND DURATION
---------------------------------------- -
R
C
8.3ms
FB
C
1.4 VID
T
RAMP
160
SS
COMP
VDIFF
IOUT
(
SS
FB
×
, is determined by an 11-bit counter
10
creates an initial offset across R
)
–
6
FB
ISL6569A INTERNAL CIRCUIT
=
I
AVG
I
560µs
RAMP
OUT
I
RAMP
ERROR AMPLIFIER
offset. This produces a
may or may not be
V
IDEAL DIODES
RAMP
FB
+
-
= 1kΩ and T
December 29, 2004
REFERENCE
VOLTAGE
RAMP
V
COMP
RAMP
(EQ. 10)
(EQ. 9)
FN9092.2
, is
FB
SS
,