ISL6569ACR Intersil, ISL6569ACR Datasheet - Page 9

• Manufacturer Part Number: ISL6569ACR
• Description: IC CTRLR PWM BUCK 2PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6569ACR

• Pwm Type: Voltage/Current Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 2MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

In addition, the peak-to-peak amplitude of the combined
inductor currents is reduced in proportion to the number of
phases. To understand the reduction of ripple current
amplitude in the multi-phase circuit, examine the equation
representing an individual channel’s peak-to-peak inductor
current.
In Equation 1, V
voltages respectively, L is the single-channel inductor value,
and f
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of two symmetrically phase-shifted inductor currents in
Equation 2.
Peak-to-peak ripple current decreases by an amount
proportional to the number of channels. Output-voltage
ripple is a function of capacitance, capacitor equivalent
series resistance (ESR), and inductor ripple current.
Reducing the inductor ripple current allows the designer to
use fewer or less costly output capacitors.
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 3 illustrates input
currents from a two-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 3 delivers 36A to a 1.5V
load from a 12V input. The RMS input capacitor current is
8.6A. Compare this to a single-phase converter also
stepping down 12V to 1.5V at 36A. The single-phase
converter has 11.9A RMS input capacitor current. The
single-phase converter input capacitor bank must support
38% more RMS current than an equivalent 2-phase
converter.
Figure 16 in the section entitled Input Capacitor Selection
can be used to determine the input-capacitor RMS current
based on load current, duty cycle. It is provided as an aid in
determining the optimal input capacitor solution.
I
I
PP
C PP
,
=
S
=
(
----------------------------------------------------- -
is the switching frequency.
V
(
---------------------------------------------------------- -
IN
V
IN
–
L f
V
–
OUT
S
2 V
L f
V
IN
S
IN
OUT
) V
V
and V
IN
OUT
) V
OUT
OUT
are the input and output
9
(EQ. 2)
(EQ. 1)
ISL6569A
PWM Operation
One switching cycle is defined as the time between PWM1
pulse termination signals. The pulse termination signal is
an internally generated clock signal which triggers the
falling edge of PWM1. The cycle time of the pulse
termination signal is the inverse of the switching frequency
set by the resistor between the FS/DIS pin and ground.
Each cycle begins when the clock signal commands the
channel-1 PWM output to go low. The PWM1 transition
signals the channel-1 MOSFET driver to turn off the
channel-1 upper MOSFET and turn on the channel-1
synchronous MOSFET. The PWM2 pulse terminates 1/2 of
a cycle after PWM1.
Once a PWM signal transitions low, it is held low for a
minimum of 1/4 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
V
sawtooth ramp as illustrated in Figure 1. When the modified
V
output transitions high. The MOSFET driver detects the
change in state of the PWM signal and turns off the
synchronous MOSFET and turns on the upper MOSFET.
The PWM signal will remain high until the pulse termination
signal marks the beginning of the next cycle by triggering
the PWM signal low.
COMP
COMP
FIGURE 3. CHANNEL INPUT CURRENTS AND INPUT-
, minus the current correction signal relative to the
voltage crosses the sawtooth ramp, the PWM
CHANNEL 1
INPUT CURRENT
10A/DIV
INPUT-CAPACITOR CURRENT, 10A/DIV
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
CHANNEL 2
CHANNEL 2
INPUT CURRENT
INPUT CURRENT
10A/DIV
10A/DIV
1µs/DIV
December 29, 2004
FN9092.2