IC CTRLR PWM 1PHASE SO-8

L6726A

Manufacturer Part NumberL6726A
DescriptionIC CTRLR PWM 1PHASE SO-8
ManufacturerSTMicroelectronics
TypeStep-Down (Buck)
L6726A datasheet
 


Specifications of L6726A

Internal Switch(s)NoSynchronous RectifierNo
Number Of Outputs1Voltage - OutputAdj to 0.8V
Frequency - Switching270kHzVoltage - Input1.5 ~ 12 V
Operating Temperature-20°C ~ 85°CMounting TypeSurface Mount
Package / Case8-SOIC (3.9mm Width)Output Current1.5 A
Input Voltage4.1 V to 13.2 VOperating Temperature Range- 40 C to + 150 C
Mounting StyleSMD/SMTFor Use With497-9046 - BOARD EVAL BASED ON L6726A497-6364 - BOARD DEMO FOR TS4995EIJT497-6259 - BOARD EVAL 1PH STPDN CONV L6726A
Lead Free Status / RoHS StatusLead free / RoHS CompliantCurrent - Output-
Power - Output-  
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L6726A
8
Application details
8.1
Output voltage selection
L6726A is capable to precisely regulate an output voltage as low as 0.8 V. In fact, the device
comes with a fixed 0.8 V internal reference that guarantees the output regulated voltage to
be within ±1% tolerance over line and temperature variations between 0 °C and 70 °C
(excluding output resistor divider tolerance, when present).
Output voltage higher than 0.8 V can be achieved by adding a resistor R
and ground. Referring to
where V
is 0.8 V.
REF
8.2
Compensation network
The control loop shown in
transconductance type with fixed gain (3.3 ms typ.). The FB voltage is regulated to the
internal reference, thus the output voltage is fixed accordingly to the output resistor divider
(when present).
Transconductance error amplifier output current generates a voltage across Z
compared to oscillator saw-tooth waveform to provide PWM signal to the driver section.
PWM signal is then transferred to the switching node with V
filtered by the output filter.
Figure 8.
PWM control loop
ΔV
OSC
The converter transfer function is the small signal transfer function between the voltage at
the output node of the EA (COMP) and V
conjugate) at frequency F
Figure
1, the steady state DC output voltage will be:
V
=
V
1
+
OUT
REF
Figure 8
is a voltage mode control loop. The error amplifier is a
V
IN
OSC
_
+
PWM
COMPARATOR
OTA
V
REF
COMP
+
_
FB
C
F
C
P
R
R
OS
F
Z
F
. This function has a double pole (complex
OUT
depending on the L-C
LC
OUT
Doc ID 12754 Rev 4
Application details
between FB pin
OS
R
FB
---------- -
R
OS
, which is
F
amplitude. This waveform is
IN
L
R
V
OUT
C
OUT
ESR
R
FB
OUTPUT
DIVIDER
resonance and a zero at F
ESR
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