IC CTRLR PWM 1PHASE SO-8

L6726A

Manufacturer Part NumberL6726A
DescriptionIC CTRLR PWM 1PHASE SO-8
ManufacturerSTMicroelectronics
TypeStep-Down (Buck)
L6726A datasheet
 


Specifications of L6726A

Internal Switch(s)NoSynchronous RectifierNo
Number Of Outputs1Voltage - OutputAdj to 0.8V
Frequency - Switching270kHzVoltage - Input1.5 ~ 12 V
Operating Temperature-20°C ~ 85°CMounting TypeSurface Mount
Package / Case8-SOIC (3.9mm Width)Output Current1.5 A
Input Voltage4.1 V to 13.2 VOperating Temperature Range- 40 C to + 150 C
Mounting StyleSMD/SMTFor Use With497-9046 - BOARD EVAL BASED ON L6726A497-6364 - BOARD DEMO FOR TS4995EIJT497-6259 - BOARD EVAL 1PH STPDN CONV L6726A
Lead Free Status / RoHS StatusLead free / RoHS CompliantCurrent - Output-
Power - Output-  
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Application details
depending on the output capacitor ESR. The DC gain of the modulator is simply the input
divided by the peak-to-peak oscillator voltage ΔV
voltage V
IN
V
is scaled and transferred to FB node by the output resistor divider.
OUT
The compensation network closes the loop joining FB and COMP node with transfer
function ideally equal to -gm
Compensation goal is to close the control loop assuring high DC regulation accuracy, good
dynamic performances and stability. To achieve this, the overall loop needs high DC gain,
high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F
should not exceed F
cross 0 dB axis with -20 dB/decade slope.
As an example,
Figure 9
Figure 9.
Example of type II compensation.
Gain
[dB]
OTA
open loop
gain
closed loop
gain
compensation
gain
converter
open loop
gain
0dB
Open loop converter singularities:
a)
F
=
LC
b)
F
ESR
Compensation Network singularities frequencies:
a)
F
=
Z
b)
F
=
P
16/35
·
Z
.
F
) can be fixed choosing the right R
0dB
/2π. To achieve a good phase margin, the control loop gain has to
SW
shows an asymptotic bode plot of a type II compensation.
F
F
Z
P
F
0dB
F
F
LC
ESR
1
--------------------------------- -
2π L C
OUT
1
=
------------------------------------------- -
2π C
ESR
OUT
1
------------------------------
2π R
C
F
F
1
------------------------------------------------- -
C
C
F
P
-------------------- -
2π R
F
C
+
C
F
P
Doc ID 12754 Rev 4
L6726A
.
OSC
; however, for stability, it
F
20log (gm·R
)
F
20log [V
/ΔV
·R
/(R
+R
)]
IN
OSC
OS
FB
OS
Log (Freq)