DK-DEV-4SE530N Altera, DK-DEV-4SE530N Datasheet - Page 20

• Manufacturer Part Number: DK-DEV-4SE530N
• Description: KIT DEV STRATIX IV FPGA 4SE530
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SE530N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV E
• Rohs Compliant: Yes
• For Use With/related Products: EP4SE530
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2605

4–4
Table 4–2. SW2 Dip Switch Settings
Table 4–3. SW4 Dip Switch Settings (Part 1 of 2)
Stratix IV E FPGA Development Kit User Guide
1
2
3
4
5
6
7
8
1
2
Switch
Switch
DIP0
DIP1
DIP2
DIP3
DIP4
DIP5
DIP6
CLK66_SEL
USER_DIPSW0
USER_DIPSW1
Board
Board
Label
Label
3. Set DIP switch bank (SW2) to match
4. Set DIP switch bank (SW4) to match
Switch 1 is a MAX II user-defined switch and has the following options:
■
■
Switch 2 is a MAX II user-defined switch and has the following options:
■
■
Switch 3 is a MAX II user-defined switch and has the following options:
■
■
Switch 4 is a MAX II user-defined switch and has the following options:
■
■
Switch 5 is a MAX II user-defined switch and has the following options:
■
■
Switch 6 is a MAX II user-defined switch and has the following options:
■
■
Switch 7 is a MAX II user-defined switch and has the following options:
■
■
Switch 8 has the following options:
■
■
Switch 1 is a user-defined switch and has the following options:
■
■
Switch 2 is a user-defined switch and has the following options:
■
■
When closed, a logic 0 is selected.
When open, a logic 1 is selected.
When closed, a logic 0 is selected.
When open, a logic 1 is selected.
When closed, a logic 0 is selected.
When open, a logic 1 is selected.
When closed, a logic 0 is selected.
When open, a logic 1 is selected.
When closed, a logic 0 is selected.
When open, a logic 1 is selected.
When closed, a logic 0 is selected.
When open, a logic 1 is selected.
When closed, a logic 0 is selected.
When open, a logic 1 is selected.
When closed, the SMA input clock is selected.
When open, the 66 Mhz clock is selected.
When closed, a logic 0 is selected.
When open, a logic 1 is selected.
When closed, a logic 0 is selected.
When open, a logic 1 is selected.
Function
Function
Table 4–2
Table 4–3
and
and
Figure
Figure
Chapter 4: Development Board Setup
4–2.
4–1.
© May 2010 Altera Corporation
Factory Default Switch Settings
Position
Position
Default
Default
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Open
Open