DK-DEV-4SE530N Altera, DK-DEV-4SE530N Datasheet - Page 41

• Manufacturer Part Number: DK-DEV-4SE530N
• Description: KIT DEV STRATIX IV FPGA 4SE530
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SE530N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV E
• Rohs Compliant: Yes
• For Use With/related Products: EP4SE530
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2605

Chapter 6: Board Test System
Using the Board Test System
The HSMC Tab
© May 2010 Altera Corporation
■
Error Control
The Error control controls display data errors detected during analysis and allow you
to insert errors:
■
■
■
■
Number of Addresses to Write and Read
The Number of addresses to write and read control determines the number of
addresses to use in each iteration of reads and writes. Valid values range from 8 to
16,777,216.
Data Type
The Data type control specifies the type of data contained in the transactions. The
following data types are available for analysis:
■
■
■
Read and Write Control
The Read and write control control specifies the type of transactions to analyze. The
following transaction types are available for analysis:
■
■
■
The HSMC tab allows you to perform loopback tests on the HSMC A and HSMC B
ports.
Write (MBps), Read (MBps), and Total (MBps)—Show the number of bytes of
data analyzed per second. The RLDRAMII bus is 36 bits wide and the frequency is
400 MHz double data rate (800 Mbps per pin), equating to a theoretical maximum
bandwidth of 3600 MBps.
Detected errors—Displays the number of data errors detected in the hardware.
Inserted errors—Displays the number of errors inserted into the transaction
stream.
Insert Error—Inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
Clear—Resets the Detected errors and Inserted errors counters to zeros.
PRBS—Selects pseudo-random bit sequences.
Memory—Selects a generic data pattern stored in the on chip memory of the
Stratix IV E device.
Math—Selects data generated from a simple math function within the FPGA
fabric.
Write then read—Selects read and write transactions for analysis.
Read only—Selects read transactions for analysis.
Write only—Selects write transactions for analysis.
Figure 6–8
shows the HSMC tab.
Stratix IV E FPGA Development Kit User Guide
6–15