DK-DEV-4SE530N Altera, DK-DEV-4SE530N Datasheet - Page 29

• Manufacturer Part Number: DK-DEV-4SE530N
• Description: KIT DEV STRATIX IV FPGA 4SE530
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SE530N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV E
• Rohs Compliant: Yes
• For Use With/related Products: EP4SE530
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2605

Chapter 6: Board Test System
Preparing the Board
Preparing the Board
Running the Board Test System
Using the Board Test System
© May 2010 Altera Corporation
1
1
With the power to the board off, perform the following steps:
1. Connect the USB cable to the board.
2. Verify the settings for the board settings DIP switch banks (SW1, SW2, and SW4)
3. Set the PGM CONFIG SELECT rotary switch (SW5) to the 1 position.
4. Verify the settings for the jumpers match
5. Turn the power to the board on. The board loads the design stored in the user
To run the application, navigate to the <install
dir>\kits\stratixIVE_4se530_fpga\examples\board_test_system directory and run
the BoardTestSystem.exe application.
On Windows, click Start > All Programs > Altera > Stratix IV E FPGA Development
Kit <version> > Board Test System to run the application.
A GUI appears, displaying the application tab that corresponds to the design running
in the FPGA. The Stratix IV E FPGA development board’s flash memory ships
preconfigured with the design that corresponds to the Config, GPIO, and
SRAM&Flash tabs.
If you power up your board with the PGM CONFIG SELECT rotary switch (SW5) in a
position other than the 1 position, or if you load your own design into the FPGA with
the Quartus II Programmer, you receive a message prompting you to configure your
board with a valid Board Test System design. Refer to
information about configuring your board.
This section describes each control in the Board Test System application.
match
determine the devices to include in the JTAG chain, among other important
default settings.
f
hardware portion of flash memory into the FPGA. If your board is still in the
factory configuration or if you have downloaded a newer version of the Board Test
System to flash memory through the Board Update Portal, the design that loads
tests accessing the GPIO, SRAM, and flash memory.
c
To ensure operating stability, keep the USB cable connected and the board
powered on when running the demonstration application. The application
cannot run correctly unless the USB cable is attached and the board is on.
Table 4–1 on page
For more information about the board’s DIP switch and jumper settings,
refer to the
Stratix IV E FPGA Development Board Reference
4–3,
Table 4–2 on page
Table 4–4 on page
4–4, and
Stratix IV E FPGA Development Kit User Guide
“The Configure Menu”
Table 4–3 on page
4–5. These settings
Manual.
for
4–4.
6–3