AT91SAM9XE512-QU Atmel, AT91SAM9XE512-QU Datasheet - Page 17
AT91SAM9XE512-QU
Manufacturer Part Number
AT91SAM9XE512-QU
Description
MCU ARM9 512K FLASH 208-PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9XE128-QU.pdf
(860 pages)
Specifications of AT91SAM9XE512-QU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Controller Family/series
AT91SAM9xxxxx
No. Of I/o's
96
Ram Memory Size
32KB
Cpu Speed
180MHz
No. Of Timers
2
Rohs Compliant
Yes
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Package
208PQFP
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
180 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
For Use With
AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9XE512-QU
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VISHAY
Quantity:
40 000
Company:
Part Number:
AT91SAM9XE512-QU
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7.2
7.2.1
7.2.2
6254C–ATARM–22-Jan-10
Bus Matrix
Matrix Masters
Matrix Slaves
The Bus Matrix of the AT91SAM9XE128/256/512 manages six Masters, thus each master can
perform an access concurrently with others, depending on whether the slave it accesses is
available.
Each Master has its own decoder, which can be defined specifically for each master. In order to
simplify the addressing, all the masters have the same decodings.
Table 7-1.
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
Table 7-2.
Master 0
Master 1
Master 2
Master 3
Master 4
Master 5
Slave 0
Slave 1
Slave 2
• 6-layer Matrix, handling requests from 6 masters
• Programmable Arbitration strategy
• Burst Management
• One Address Decoder provided per Master
• Boot Mode Select
• Remap Command
– Fixed-priority Arbitration
– Round-Robin Arbitration, either with no default master, last accessed default master
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
– Three different slaves may be assigned to each decoded memory area: one for
– Non-volatile Boot Memory can be internal ROM or internal Flash
– Selection is made by General purpose NVM bit sampled at reset
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
or fixed default master
internal ROM boot, one for internal flash boot, one after remap
(ROM or Flash)
List of Bus Matrix Masters
List of Bus Matrix Slaves
AT91SAM9XE128/256/512 Preliminary
Internal SRAM
Internal ROM
USB Host User Interface
External Bus Interface
ARM926
ARM926 Data
Peripheral DMA Controller
USB Host Controller
Image Sensor Controller
Ethernet MAC
™
Instruction
17
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