AT91SAM9XE512-QU Atmel, AT91SAM9XE512-QU Datasheet - Page 52
![MCU ARM9 512K FLASH 208-PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT91SAM9XE512-QU
Manufacturer Part Number
AT91SAM9XE512-QU
Description
MCU ARM9 512K FLASH 208-PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9XE128-QU.pdf
(860 pages)
Specifications of AT91SAM9XE512-QU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Controller Family/series
AT91SAM9xxxxx
No. Of I/o's
96
Ram Memory Size
32KB
Cpu Speed
180MHz
No. Of Timers
2
Rohs Compliant
Yes
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Package
208PQFP
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
180 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
For Use With
AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9XE512-QU
Manufacturer:
VISHAY
Quantity:
40 000
Company:
Part Number:
AT91SAM9XE512-QU
Manufacturer:
Atmel
Quantity:
58
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11.3.9
11.3.10
52
AT91SAM9XE128/256/512 Preliminary
New ARM Instruction Set
Thumb Instruction Set Overview
.
Table 11-3.
Notes:
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
Table 11-3
ence Manual referenced in
Table 11-4
Table 11-4.
Mnemonic
Mnemonic
MOV
ADD
SUB
CMP
TST
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store multiple instructions
• Exception-generating instruction
SMULWy
SMLAWy
SMLAxy
SMULxy
QDADD
QDSUB
SMLAL
BLX
QADD
QSUB
BXJ
1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
(1)
gives the Thumb instruction mnemonic list.
shows the Thumb instruction set, for further details, see the ARM Technical Refer-
New ARM Instruction Mnemonic List
Thumb Instruction Mnemonic List
Operation
Branch and exchange to Java
Branch, Link and exchange
Signed Multiply Accumulate 16 *
16 bit
Signed Multiply Accumulate Long
Signed Multiply Accumulate 32 *
16 bit
Signed Multiply 16 * 16 bit
Signed Multiply 32 * 16 bit
Saturated Add
Saturated Add with Double
Saturated subtract
Saturated Subtract with double
Operation
Move
Add
Subtract
Compare
Test
Table 11-1 on page
43.
Mnemonic
MVN
ADC
SBC
CMN
NEG
Mnemonic
MRRC
MCRR
MCR2
CDP2
STRD
LDRD
BKPT
STC2
LDC2
PLD
CLZ
Operation
Move Not
Add with Carry
Subtract with Carry
Compare Negated
Negate
Operation
Move double from coprocessor
Alternative move of ARM reg to
coprocessor
Move double to coprocessor
Alternative Coprocessor Data
Processing
Breakpoint
Soft Preload, Memory prepare to
load from address
Store Double
Alternative Store from
Coprocessor
Load Double
Count Leading Zeroes
Alternative Load to Coprocessor
6254C–ATARM–22-Jan-10
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