AT91SAM9XE512-QU Atmel, AT91SAM9XE512-QU Datasheet - Page 842
![MCU ARM9 512K FLASH 208-PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT91SAM9XE512-QU
Manufacturer Part Number
AT91SAM9XE512-QU
Description
MCU ARM9 512K FLASH 208-PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9XE128-QU.pdf
(860 pages)
Specifications of AT91SAM9XE512-QU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Controller Family/series
AT91SAM9xxxxx
No. Of I/o's
96
Ram Memory Size
32KB
Cpu Speed
180MHz
No. Of Timers
2
Rohs Compliant
Yes
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Package
208PQFP
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
180 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
For Use With
AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9XE512-QU
Manufacturer:
VISHAY
Quantity:
40 000
Company:
Part Number:
AT91SAM9XE512-QU
Manufacturer:
Atmel
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46.2.8
46.2.8.1
46.2.8.2
46.2.9
46.2.9.1
46.2.9.2
842
AT91SAM9XE128/256/512 Preliminary
Two-wire Interface (TWI)
USB Host Port (UHP)
TWI: Software Reset
TWI: Overrun in Master Read Mode
UHP: Non-ISO IN transfers
UHP: ISO OUT Transfers
The RXRDY Flag is not reset when a software reset is performed.
None.
When the shift register and the receive holding register (RHR) are full and TWI reads new data,
then an overrun error occurs.
None.
Conditions:
Consider the following sequence:
Consequence: When this defect manifests itself, the Host controller re-attempts the same IN
token.
This problem can be avoided if the system guarantees that the status update can be completed
within the same frame.
Conditions:
Consider the following sequence:
1. The Host controller issues an IN token.
2. The Device provides the IN data in a short packet.
3. The Host controller writes the received data to the system memory.
4. The Host controller is now supposed to carry out two Write transactions (TD status
5. The Host controller raises the request for the first write transaction. By the time the
6. After completing the first write transaction, the Host controller skips the second write
1. The Host controller sends an ISO OUT token after fetching 16 bytes of data from the
2. When the Host controller is sending the ISO OUT data, because of system latencies,
3. While there is an underrun condition, if the Host controller is in the process of bit-stuff-
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
write and TD retirement write) to the system memory in order to complete the status
update.
transaction is completed, a frame boundary is crossed.
transaction.
system memory.
remaining bytes of the packet are not available. This results in a buffer underrun
condition.
ing, it causes the Host controller to hang.
6254C–ATARM–22-Jan-10
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