AT91SAM9XE512-QU Atmel, AT91SAM9XE512-QU Datasheet - Page 66

• Manufacturer Part Number: AT91SAM9XE512-QU
• Description: MCU ARM9 512K FLASH 208-PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE512-QU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Controller Family/series: AT91SAM9xxxxx
• No. Of I/o's: 96
• Ram Memory Size: 32KB
• Cpu Speed: 180MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Package: 208PQFP
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.6.4
12.6.4.1
66
AT91SAM9XE128/256/512 Preliminary
IEEE 1149.1 JTAG Boundary Scan
JTAG Boundary-scan Register
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging
technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST
and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds
with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1
JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per-
formed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
The Boundary-scan Register (BSR) contains 484 bits that correspond to active pins and associ-
ated control signals.
Each AT91SAM9XE input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT
bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data
applied to the pad. The CONTROL bit selects the direction of the pad.
Table 12-2.AT91SAM9XE JTAG Boundary Scan Register
Bit Number
307
306
305
304
303
302
301
300
299
298
297
296
295
294
293
292
291
290
289
288
287
286
Pin Name
A10
A11
A12
A13
A14
A15
A16
A17
A18
A0
A1
Pin Type
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
Associated BSR Cells
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
6254C–ATARM–22-Jan-10
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL