AT91SAM9XE512-QU Atmel, AT91SAM9XE512-QU Datasheet - Page 315

MCU ARM9 512K FLASH 208-PQFP

AT91SAM9XE512-QU

Manufacturer Part Number
AT91SAM9XE512-QU
Description
MCU ARM9 512K FLASH 208-PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM9XE512-QU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Controller Family/series
AT91SAM9xxxxx
No. Of I/o's
96
Ram Memory Size
32KB
Cpu Speed
180MHz
No. Of Timers
2
Rohs Compliant
Yes
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Package
208PQFP
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
180 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
For Use With
AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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27. Clock Generator
27.1
27.2
27.3
6254C–ATARM–22-Jan-10
Description
Clock Generator Block Diagram
Slow Clock Crystal Oscillator
The Clock Generator is made up of 2 PLL, a Main Oscillator, as well as an RC Oscillator and a
32,768 Hz low-power Oscillator.
It provides the following clocks:
The Clock Generator User Interface is embedded within the Power Management Controller one
and is described in
Figure 27-1. Clock Generator Block Diagram
The Clock Generator integrates a 32,768 Hz low-power oscillator. The XIN32 and XOUT32 pins
must be connected to a 32,768 Hz crystal. Two external capacitors must be wired as shown in
Figure
• SLCK, the Slow Clock, which is the only permanent clock within the system
• MAINCK is the output of the Main Oscillator
• PLLACK is the output of the Divider and PLL A block
• PLLBCK is the output of the Divider and PLL B block
27-2.
Section
AT91SAM9XE128/256/512 Preliminary
OSC_SEL
XOUT32
PLLRCA
28.9. However, the Clock Generator registers are named CKGR_.
XIN32
XOUT
XIN
Clock Generator
Management
Slow Clock
Controller
On Chip
RC OSC
Oscillator
Oscillator
Status
PLL and
Divider A
PLL and
Divider B
Power
Main
Control
Main Clock
MAINCK
PLLA Clock
PLLACK
PLLB Clock
PLLBCK
Slow Clock
SLCK
315

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