AT91SAM9XE512-QU Atmel, AT91SAM9XE512-QU Datasheet - Page 87
![MCU ARM9 512K FLASH 208-PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT91SAM9XE512-QU
Manufacturer Part Number
AT91SAM9XE512-QU
Description
MCU ARM9 512K FLASH 208-PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9XE128-QU.pdf
(860 pages)
Specifications of AT91SAM9XE512-QU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Controller Family/series
AT91SAM9xxxxx
No. Of I/o's
96
Ram Memory Size
32KB
Cpu Speed
180MHz
No. Of Timers
2
Rohs Compliant
Yes
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Package
208PQFP
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
180 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
For Use With
AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9XE512-QU
Manufacturer:
VISHAY
Quantity:
40 000
Company:
Part Number:
AT91SAM9XE512-QU
Manufacturer:
Atmel
Quantity:
58
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14.2.3
14.2.4
14.2.4.1
6254C–ATARM–22-Jan-10
Entering Programming Mode
Programmer Handshaking
Write Handshaking
Table 14-3.
The following algorithm puts the device in Parallel Programming Mode:
Note:
An handshake is defined for read and write operations. When the device is ready to start a new
operation (RDY signal set), the programmer starts the handshake by clearing the NCMD signal.
The handshaking is achieved once NCMD signal is high and RDY is high.
For details on the write handshaking sequence, refer to
DATA[15:0]
0x0011
0x0012
0x0022
0x0032
0x0042
0x0013
0x0014
0x0024
0x0015
0x0034
0x0044
0x0025
0x0054
0x0035
0x001F
0x001E
• Apply GND, VDDIO, VDDCORE and VDDPLL.
• Apply XIN clock within T
• Wait for T
• Start a read or write handshaking.
After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an
external clock ( > 32 kHz) is connected to XIN, then the device switches on the external clock.
Else, XIN input is not considered. A higher frequency on XIN speeds up the programmer
handshake.
POR_RESET
Command Bit Coding
Symbol
READ
WP
WPL
EWP
EWPL
EA
SLB
CLB
GLB
SGPB
CGPB
GGPB
SSE
WRAM
GSE
GVE
AT91SAM9XE128/256/512 Preliminary
POR_RESET
if an external clock is available.
Command Executed
Read Flash
Write Page Flash
Write Page and Lock Flash
Erase Page and Write Page
Erase Page and Write Page then Lock
Erase All
Set Lock Bit
Clear Lock Bit
Get Lock Bit
Set General Purpose NVM bit
Clear General Purpose NVM bit
Get General Purpose NVM bit
Set Security Bit
Get Security Bit
Write Memory
Get Version
Figure 14-2
and
Table
14-4.
87
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