AT91SAM9XE512-QU Atmel, AT91SAM9XE512-QU Datasheet - Page 57
![MCU ARM9 512K FLASH 208-PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT91SAM9XE512-QU
Manufacturer Part Number
AT91SAM9XE512-QU
Description
MCU ARM9 512K FLASH 208-PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9XE128-QU.pdf
(860 pages)
Specifications of AT91SAM9XE512-QU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Controller Family/series
AT91SAM9xxxxx
No. Of I/o's
96
Ram Memory Size
32KB
Cpu Speed
180MHz
No. Of Timers
2
Rohs Compliant
Yes
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Package
208PQFP
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
180 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
For Use With
AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
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Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9XE512-QU
Manufacturer:
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Quantity:
40 000
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AT91SAM9XE512-QU
Manufacturer:
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11.5.3
11.5.4
6254C–ATARM–22-Jan-10
Translation Table Walk Hardware
MMU Faults
fied Virtual Address), the access control logic determines if the access is permitted and outputs
the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU
signals the CPU core to abort.
If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked
to retrieve the translation information from the translation table in physical memory.
The translation table walk hardware is a logic that traverses the translation tables located in
physical memory, gets the physical address and access permissions and updates the TLB.
The number of stages in the hardware table walking is one or two depending whether the
address is marked as a section-mapped access or a page-mapped access.
There are three sizes of page-mapped accesses and one size of section-mapped access. Page-
mapped accesses are for large pages, small pages and tiny pages. The translation process
always begins with a level one fetch. A section-mapped access requires only a level one fetch,
but a page-mapped access requires an additional level two fetch. For further details on the
MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual.
The MMU generates an abort on the following types of faults:
The access control mechanism of the MMU detects the conditions that produce these faults. If
the fault is a result of memory access, the MMU aborts the access and signals the fault to the
CPU core.The MMU retains status and address information about faults generated by the data
accesses in the data fault status register and fault address register. It also retains the status of
faults generated by instruction fetches in the instruction fault status register.
The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and
the domain number of the aborted access when it happens. The fault address register (register 6
in CP15) holds the MVA associated with the access that caused the Data Abort. For further
details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual.
• Alignment faults (for data accesses only)
• Translation faults
• Domain faults
• Permission faults
AT91SAM9XE128/256/512 Preliminary
57
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