AT91SAM9XE512-QU Atmel, AT91SAM9XE512-QU Datasheet - Page 18
![MCU ARM9 512K FLASH 208-PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT91SAM9XE512-QU
Manufacturer Part Number
AT91SAM9XE512-QU
Description
MCU ARM9 512K FLASH 208-PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9XE128-QU.pdf
(860 pages)
Specifications of AT91SAM9XE512-QU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Controller Family/series
AT91SAM9xxxxx
No. Of I/o's
96
Ram Memory Size
32KB
Cpu Speed
180MHz
No. Of Timers
2
Rohs Compliant
Yes
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Package
208PQFP
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
180 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
For Use With
AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9XE512-QU
Manufacturer:
VISHAY
Quantity:
40 000
Company:
Part Number:
AT91SAM9XE512-QU
Manufacturer:
Atmel
Quantity:
58
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7.2.3
Table 7-3.
7.3
18
Slave
0
1
2
3
4
Peripheral DMA Controller
Internal SRAM
Internal ROM
UHP User Interface
External Bus Interface
Internal Flash
Internal Peripherals
Reserved
AT91SAM9XE128/256/512 Preliminary
Masters to Slaves Access
Masters to Slaves Access
Table 7-2.
All the Masters can normally access all the Slaves. However, some paths do not make sense,
such as allowing access from the Ethernet MAC to the internal peripherals.
Thus, these paths are forbidden or simply not wired, and shown as “–” in the following table.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Slave 3
Slave 4
Slave 5
• Acting as one Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
• Next Pointer Support, forbids strong real-time constraints on buffer management.
• Twenty-four channels
Master
of the processor.
– Two for each USART
– Two for the Debug Unit
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– Two for the Two Wire Interface
– One for Multimedia Card Interface
– One for Analog To Digital Converter
– TWI0 Transmit Channel
– TWI1 Transmit Channel
– DBGU Transmit Channel
– USART4 Transmit Channel
– USART3 Transmit Channel
ARM926 Instruction
List of Bus Matrix Slaves (Continued)
and Data
0 and 1
X
X
X
X
X
X
–
Internal Flash
Internal Peripherals
Reserved
Periphera DMA
Controller
X
X
X
X
2
–
–
–
ISI Controller
X
X
3
–
–
–
–
–
Ethernet MAC
X
X
X
4
–
–
–
–
6254C–ATARM–22-Jan-10
USB Host
Controller
X
X
5
–
–
–
–
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