AT91SAM9XE512-QU Atmel, AT91SAM9XE512-QU Datasheet - Page 305
![MCU ARM9 512K FLASH 208-PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT91SAM9XE512-QU
Manufacturer Part Number
AT91SAM9XE512-QU
Description
MCU ARM9 512K FLASH 208-PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9XE128-QU.pdf
(860 pages)
Specifications of AT91SAM9XE512-QU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Controller Family/series
AT91SAM9xxxxx
No. Of I/o's
96
Ram Memory Size
32KB
Cpu Speed
180MHz
No. Of Timers
2
Rohs Compliant
Yes
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Package
208PQFP
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
180 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
For Use With
AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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26.3.2
26.3.3
6254C–ATARM–22-Jan-10
Memory Pointers
Transfer Counters
transmit and receive parts of a full duplex peripheral can be programmed at the same time,
whereas only one part (transmit or receive) of a half duplex peripheral can be programmed at a
time.
32-bit pointers define the access location in memory for current and next transfer, whether it is
for read (transmit) or write (receive). 16-bit counters define the size of current and next transfers.
It is possible, at any moment, to read the number of transfers left for each channel.
The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for
each channel. The status for each channel is located in the associated peripheral status register.
Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in
the peripheral’s Transfer Control Register.
At the end of a transfer, the PDC channel sends status flags to its associated peripheral. These
flags are visible in the peripheral status register (ENDRX, ENDTX, RXBUFF, and TXBUFE).
Refer to
Each full duplex peripheral is connected to the PDC by a receive channel and a transmit chan-
nel. Both channels have 32-bit memory pointers that point respectively to a receive area and to
a transmit area in on- and/or off-chip memory.
Each half duplex peripheral is connected to the PDC by a bidirectional channel. This channel
has two 32-bit memory pointers, one for current transfer and the other for next transfer. These
pointers point to transmit or receive data depending on the operating mode of the peripheral.
Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented
respectively by 1, 2 or 4 bytes.
If a memory pointer address changes in the middle of a transfer, the PDC channel continues
operating using the new address.
Each channel has two 16-bit counters, one for current transfer and the other one for next trans-
fer. These counters define the size of data to be transferred by the channel. The current transfer
counter is decremented first as the data addressed by current memory pointer starts to be trans-
ferred. When the current transfer counter reaches zero, the channel checks its next transfer
counter. If the value of next counter is zero, the channel stops transferring data and sets the
appropriate flag. But if the next counter value is greater then zero, the values of the next
pointer/next counter are copied into the current pointer/current counter and the channel resumes
the transfer whereas next pointer/next counter get zero/zero as values. At the end of this trans-
fer the PDC channel sets the appropriate flags in the Peripheral Status Register.
The following list gives an overview of how status register flags behave depending on the
counters’ values:
These status flags are described in the Peripheral Status Register.
• ENDRX flag is set when the PERIPH_RCR register reaches zero.
• RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.
• ENDTX flag is set when the PERIPH_TCR register reaches zero.
• TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero.
Section 26.3.3
AT91SAM9XE128/256/512 Preliminary
and to the associated peripheral user interface.
305
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