P87C591VFA/00,512 NXP Semiconductors, P87C591VFA/00,512 Datasheet - Page 28

• Manufacturer Part Number: P87C591VFA/00,512
• Description: IC 80C51 MCU 16K OTP 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C591VFA/00,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: CAN, EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN, I2C, UART
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1256-5; 935268182512; P87C591VFAA

Philips Semiconductors
Table 10 CAN Special Function Registers
12.3.2
This read/write register defines the address of one of the
PeliCAN internal registers to be accessed via CANDAT. It
could be interpreted as a pointer to the PeliCAN.
The read and write access to the PeliCAN Block register is
performed using the CANDAT register.
With the implemented auto address increment mode a fast
stack-like reading and writing of CAN controller internal
registers is provided. If the currently defined address
within CANADR is above or equal to 32 decimal, the
content of CANADR is incremented automatically after any
read or write access to CANDAT. For instance, loading a
message into the Transmit Buffer can be done by writing
the first Transmit Buffer Address (112 decimal) into
CANADR and then moving byte by byte of the message to
CANDAT. Incrementing CANADR beyond FFh resets
CANADR to 00h.
In case CANADR is below 32 decimal, there is no
automatic address incrementation performed. CANADR
keeps its value even if CANDAT is accessed for reading or
writing. This is to allow polling of registers in the lower
address space of the PeliCAN controller.
12.3.3
CANDAT is implemented as a read/write register.
The Special Function Register CANDAT appears as a port
to the CAN controller’s internal register (memory location)
being selected by CANADR. Reading or writing CANDAT
is effectively an access to that PeliCAN internal register,
2000 Jul 26
CANMOD
CANCON
CANADR
CANDAT
CANSTA
Single-chip 8-bit microcontroller with CAN controller
SFR
CANADR
CANDAT R
ACCESS
Read/
Read/
Read/
Read
Read
Write
Write
Write
Write
Write
EGISTER
-
-
Mode
Status
Interrupt
Enable
Interrupt
Command
PELICAN
REG.
CANA7 CANA6 CANA5 CANA4 CANA3 CANA2 CANA1 CANA0
CAND7 CAND6 CAND5 CAND4 CAND3 CAND2 CAND1 CAND0
BEIE
BIT7
BEI
TM
BS
-
RIPM
BIT6
ALIE
ALI
ES
-
RPM
EPIE
BIT5
EPI
TS
28
-
which is selected by CANADR. CANDAT is implemented
as a read/write register.
Note that any access to this register automatically
increments CANADR if the current address within
CANADR is above or equal to 32 decimal.
12.3.4
With a read or write access to CANMOD the Mode
Register of the PeliCAN is accessed directly. The Mode
register is located at address 00h within the PeliCAN
Block.
12.3.5
The CANSTA SFR provides a direct access to the Status
Register of the PeliCAN as well as to the Interrupt Enable
Register, depending on the direction of the access.
Reading CANSTA is an access to the Status Register of
the PeliCAN (address 2). When writing to CANSTA the
Interrupt Enable Register is accessed (address 4).
12.3.6
The CANCON SFR provides a direct access to the
Interrupt Register of the PeliCAN as well as to the
Command register, depending on the direction of the
access.
When reading CANCON the Interrupt Register of the
PeliCAN is accessed (address 3), while writing to
CANCON means an access to the Command Register
(address 1).
WUIE
BIT4
SRR
WUI
SM
RS
CANMOD
CANSTA
CANCON
DOIE
CDO
BIT3
TCS
DOI
BIT2
STM
RRB
TBS
EIE
EI
Preliminary Specification
BIT1
LOM
DOS
TIE
AT
TI
P8xC591
BIT0
RBS
RIE
RM
TR
RI
ADDR
SFR
C1
C2
C4
C0
C3