P87C591VFA/00,512 NXP Semiconductors, P87C591VFA/00,512 Datasheet - Page 36

• Manufacturer Part Number: P87C591VFA/00,512
• Description: IC 80C51 MCU 16K OTP 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C591VFA/00,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: CAN, EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN, I2C, UART
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1256-5; 935268182512; P87C591VFAA

Philips Semiconductors
5. If the Transmission Request or the Self Reception Request bit was set ‘1’ in a previous command, it cannot be
6. Setting the command bits CMR.0 and CMR.1 simultaneously results in transmitting a message once. No
12.5.4
The content of the Status Register reflects the status of the CAN controller. The Status Register appears to the CPU as
a read only memory.
Table 15 Status Register (SR) CAN Addr. 2, bit interpretation
2000 Jul 26
SR.7
SR.6
SR.5
SR.4
SR.3
SR.2
SR.1
SR.0
Single-chip 8-bit microcontroller with CAN controller
BIT
cancelled by resetting the bits. The requested transmission may only be cancelled by setting the Abort Transmission
bits.
re-transmission will be performed in case of an error or arbitration lost (single shot transmission). Setting the
command bits CMR.4 and CMR.1 simultaneously results in sending the transmit message once using the self
reception feature. No re-transmission will be performed in case of an error or arbitration lost. Setting the command
bits CMR.0, CMR.1 and CMR.4 simultaneously results in transmitting a message once as described for CMR.0 and
CMR.1. The moment the Transmit Status bit is set within the Status Register, the internal Transmission Request Bit
is cleared automatically. Setting CMR.0 and CMR.4 simultaneously will ignore the set CMR.4 bit.
S
TATUS
SYMBOL
DOS
RBS
TCS
TBS
RS
BS
ES
TS
R
EGISTER
Bus Status; Note 1
Error Status; Note 2
Transmit Status;
Note 3
Receive Status;
Note 3
Transmission
Complete Status;
Note 4
Transmit Buffer
Status; Note 5
Data Overrun Status;
Note 6
Receive Buffer
Status; Note 7
(SR)
NAME
1 (Bus-Off)
0 (Bus-On)
1 (error)
0 (ok)
1 (transmit)
0 (idle)
1 (receive)
0 (idle)
1 (complete)
0 (incomplete)
1 (released)
0 (locked)
1 (overrun)
0 (absent)
1 (full)
0 (empty)
VALUE
36
The CAN controller is not involved in bus activities.
The CAN controller is involved in bus activities
At least one of the error counters has reached or
exceeded the CPU warning limit.
Both error counters are below the warning limit.
The CAN controller is transmitting a message.
The CAN controller is receiving a message.
Last requested transmission has been successfully
completed.
Previously requested transmission is not yet
completed.
The CPU may write a message into the Transmit
Buffer.
The CPU cannot access the Transmit Buffer. A
message is either waiting for transmission or is in
transmitting process.
A message was lost because there was not enough
space for that message in the RXFIFO.
No data overrun has occurred since the last Clear Data
Overrun command was given
One or more complete messages are available in the
RXFIFO.
No message is available.
FUNCTION
Preliminary Specification
P8xC591