P87C591VFA/00,512 NXP Semiconductors, P87C591VFA/00,512 Datasheet - Page 78

• Manufacturer Part Number: P87C591VFA/00,512
• Description: IC 80C51 MCU 16K OTP 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C591VFA/00,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: CAN, EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN, I2C, UART
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1256-5; 935268182512; P87C591VFAA

Philips Semiconductors
15.2.5
In the master transmitter mode, the arbitration logic checks
that every transmitted logic 1 actually appears as a logic 1
on the I
logic 1 and pulls the SDA line low, arbitration is lost, and
SIO1 immediately changes from master transmitter to
slave receiver. SIO1 will continue to output clock pulses
(on SCL) until transmission of the current serial byte is
complete.
Arbitration may also be lost in the master receiver mode.
Loss of arbitration in this mode can only occur while SIO1
is returning a not acknowledge: (logic 1) to the bus.
Arbitration is lost when another device on the bus pulls this
signal LOW. Since this can occur only at the end of a serial
byte, SIO1 generates no further clock pulses. Figure 33
shows the arbitration procedure.
2000 Jul 26
handbook, full pagewidth
Single-chip 8-bit microcontroller with CAN controller
2
C bus. If another device on the bus overrules a
A
RBITRATION AND
SDA
SCL
(1) Another device transmits identical serial data.
(2) Another device overrules a logic 1 (dotted line) transmitted by SIO1 (master) by pulling the SDA line low. Arbitration is lost,
(3) SIO1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. SIO1 will not
and SIO1 enters the slave receiver mode.
generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration.
S
YNCHRONIZATION
1
(1)
L
Fig.33 Arbitration Procedure.
OGIC
2
(1)
3
78
(2)
The synchronization logic will synchronize the serial clock
generator with the clock pulses on the SCL line from
another device. If two or more master devices generate
clock pulses, the mark duration is determined by the
device that generates the shortest marks, and the space
duration is determined by the device that generates the
longest spaces. Figure 34 shows the synchronization
procedure.
A slave may stretch the space duration to slow down the
bus master. The space duration may also be stretched for
handshaking purposes. This can be done after each bit or
after a complete byte transfer. SIO1 will stretch the SCL
space duration after a byte has been transmitted or
received and the acknowledge bit has been transferred.
The serial interrupt flag (SI) is set, and the stretching
continues until the serial interrupt flag is cleared.
4
(3)
8
Preliminary Specification
ACK
9
P8xC591
MHI034