MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet - Page 35

• Manufacturer Part Number: MC908GZ60CFJE
• Description: IC MCU 60K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GZ60CFJE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: CAN, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
$000A
$000B
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
Addr.
Data Direction Register C
Data Direction Register D
Data Direction Register A
Data Direction Register B
ESCI Prescaler Register
Register Name
Port C Data Register
Port D Data Register
Port A Data Register
Port B Data Register
Port E Data Register
ESCI Arbiter Control
Register (SCIADAT)
Register (SCIACTL)
ESCI Arbiter Data
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MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 9)
(SCPSC)
(DDRC)
(DDRD)
(DDRA)
(DDRB)
(PTC)
(PTD)
(PTA)
(PTB)
(PTE)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
DDRA7
DDRB7
DDRD7
PTD7
PDS2
ARD7
PTA7
PTB7
Bit 7
AM1
1
0
0
0
0
0
0
0
0
0
= Unimplemented
DDRC6
DDRD6
DDRA6
DDRB6
ALOST
ARD6
PTA6
PTB6
PTC6
PTD6
PDS1
6
0
0
0
0
0
0
0
0
DDRC5
DDRD5
DDRA5
DDRB5
PDS0
ARD5
PTA5
PTB5
PTC5
PTD5
PTE5
AM0
5
0
0
0
0
0
0
0
R = Reserved
DDRA4
DDRB4
DDRC4
DDRD4
PSSB4
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
ACLK
ARD4
PTA4
PTB4
PTC4
PTD4
PTE4
4
0
0
0
0
0
0
0
DDRA3
DDRB3
DDRC3
DDRD3
PSSB3
PTD3
ARD3
PTA3
PTB3
PTC3
PTE3
AFIN
3
0
0
0
0
0
0
0
U = Unaffected
DDRA2
DDRB2
DDRC2
DDRD2
PSSB2
ARUN
ARD2
PTC2
PTD2
PTE2
PTA2
PTB2
Input/Output (I/O) Section
2
0
0
0
0
0
0
0
AROVFL
DDRC1
DDRD1
DDRA1
DDRB1
PSSB1
ARD1
PTA1
PTB1
PTC1
PTD1
PTE1
1
0
0
0
0
0
0
0
DDRC0
DDRD0
DDRA0
DDRB0
PSSB0
ARD8
ARD0
PTA0
PTB0
PTC0
PTD0
PTE0
Bit 0
0
0
0
0
0
0
0
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