MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet - Page 40

• Manufacturer Part Number: MC908GZ60CFJE
• Description: IC MCU 60K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GZ60CFJE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: CAN, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory
40
$003C
$003D
$003E
$003F
$0440
$0441
$0444
$0445
$0448
Addr.
$0456
$0457
$0458
TIM2 Channel 2 Status and
Data Direction Register G
Control Register (T2SC2)
Data Direction Register F
ADC Data High Register
Register High (T2CH2H)
ADC Status and Control
ADC Data Low Register
Register Low (T2CH2L)
Register Name
Port G Data Register
Port F Data Register
ADC Clock Register
Keyboard Interrupt
Register (ADSCR)
Polarity Register
TIM2 Channel 2
TIM2 Channel 2
See page 185.
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See page 121.
See page 297.
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(INTKBIPR)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 9)
(ADCLK)
(DDRG)
(ADRH)
(DDRF)
(ADRL)
(PTG)
(PTF)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
DDRG7
DDRF7
COCO
ADIV2
KBIP7
PTG7
CH2F
Bit 15
PTF7
Bit 7
AD7
Bit 7
R
0
0
0
0
0
0
0
0
= Unimplemented
DDRG6
DDRF6
ADIV1
KBIP6
CH2IE
PTG6
AIEN
PTF6
AD6
14
6
0
0
0
0
0
0
0
6
DDRG5
DDRF5
ADCO
ADIV0
KBIP5
PTG5
MS2B
PTF5
AD5
13
5
0
0
0
0
0
0
0
5
R = Reserved
Indeterminate after reset
Indeterminate after reset
ADICLK
ADCH4
DDRG4
DDRF4
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
KBIP4
PTG4
MS2A
PTF4
AD4
12
4
1
0
0
0
0
0
0
4
MODE1
ADCH3
DDRG3
DDRF3
PTAF3
ELS2B
KBIP3
PTG3
A3
11
3
1
0
0
0
0
0
0
3
U = Unaffected
MODE0
DDRG2
ADCH2
DDRF2
ELS2A
KBIP2
PTG2
PTF2
AD2
10
2
1
0
1
0
0
0
0
2
Freescale Semiconductor
DDRG1
ADCH1
DDRF1
KBIP1
PTG1
TOV2
PTF1
AD9
AD1
R
1
1
0
0
0
0
0
9
1
CH2MAX
DDRG0
ADCH0
DDRF0
KBIP0
PTG0
PTF0
Bit 0
Bit 8
Bit 0
AD8
AD0
1
0
0
0
0
0
0