MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1020
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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READI Module
24.9
This section details the data trace mechanism supported by READI. Data trace is implemented via data
write messaging (DWM) and data read messaging (DRM), as per the IEEE-ISTO 5001 - 1999.
24.9.1
The L-bus allows the RCPU to perform loads and stores, and the L2U to read and write the L-bus
resources. Snooping for data trace on the L-bus requires the READI module to handle the full range of
L-bus cycles. This includes various cases of pipelining and aborted cycles.
Data trace requires snooping the L-bus cycles, and storing the information for qualifying accesses (based
on enabled features and matching target addresses). The READI module traces all data accesses that meet
the selected range and attributes. This includes all RCPU initiated accesses and all L-bus accesses.
L-bus data cycles can have data sizes of 8, 16, or 32 bits.The READI module supports all three data sizes.
In full port mode, 16-bit accesses shift out 24 bits of data so the tool can differentiate them from 8-bit
accesses.
24.9.2
Data trace messages are of five types:
24.9.2.1
The data write message contains the data write value and the address of the target location, relative to the
previous data trace message.
The data write message has the following format:
24-52
•
•
•
•
•
Data write
Data read
Data write synchronization
Data read synchronization
Error message
Data Trace
Data Trace for the Load/Store Bus (L-Bus)
Data Trace Message Formats
Data Write Message
In early versions of the READI module, 8-bit data cannot be differentiated
from 16-bit data when the 8 MSBs are set to zero. See the device mask set
errata list for customer information.
TCODE (5)
[6 bits]
Figure 24-44. Data Write Message Format
MPC561/MPC563 Reference Manual, Rev. 1.2
Max Length = 63 bits
Relative Address
Min Length = 15 bits
[1 to 25 bits]
NOTE
[8, 16, or 32 bits]
Data Value
Freescale Semiconductor
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