MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 549
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Table 14-4
multiplexer chips using one QADC module.
14.3
The QADC64E has three global registers for configuring module operation.
These global registers are always defined to be in supervisor-only data space. Refer to
QADC64E_A Address Map and
“Supervisor/Unrestricted Address
The remaining five registers in the control register block control the operation of the queuing mechanism,
and provide a means of monitoring the operation of the QADC64E.
The Conversion Command Word (CCW) table contains 64 entries to hold the software programmable
analog conversion sequences. Each CCW table entry is a 16-bit entry, though only 10 bits are used.
The final block of address space belongs to the result word table, which appears in three places in the
memory map. Each result word table location holds one 10-bit conversion value.
Freescale Semiconductor
•
•
•
•
•
•
•
The module configuration register, QADCMCR
Configuration
The interrupt register, QADCINT
The test register, QADCTEST. This register is used for factory test only.
Control register 0 (QACR0) contains hardware configuration information
“Control Register
Control register 1 (QACR1) is associated with queue 1
Control register 2 (QACR2) is associated with queue 2
Status registers (QASR0 and QASR1) provide visibility on the status of each queue and the
particular conversion that is in progress
Programming the QADC64E Registers
shows the total number of analog input channels supported with zero to four external
No External
If a QADC64E module is in external multiplexing (EMUX) mode then the
multiplexer address signal channels AN[52:54] should not be programmed
into queues.
MUX Chips
16
Register”)
0”)
Directly Connected + External Multiplexed = Total Channels
NOTE: QADC64E External MUX Users
One External
MUX Chip
MPC561/MPC563 Reference Manual, Rev. 1.2
Number of Analog Input Channels Available
Table 14-2
Space” for access modes for these registers.
20
Table 14-4. Analog Input Channels
(Section 14.3.2, “QADC64E Interrupt
for QADC64E_B Address Map. See
Two External
(Section 14.3.8, “Status Registers (QASR0 and
MUX Chips
27
(Section 14.3.1, “QADC64E Module
Three External
(Section 14.3.6, “Control Register
(Section 14.3.7, “Control Register
MUX Chips
34
QADC64E Enhanced Mode Operation
Four External
MUX Chips
Register”)
Section 14.3.1.4,
(Section 14.3.5,
41
Table 14-1
QASR1)”)
1”)
2”)
for the
14-7
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