MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 461

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Any word, half-word or byte access to a 32-bit location within the UIMB interface register decode block
that is unimplemented (defined as reserved) causes the UIMB interface to assert a data error exception on
the U-bus.The entire 32-bit location must be defined as reserved in order for a data error exception to be
asserted.
Unimplemented bits in a register return zero when read.
12.5.1
The UIMB module configuration register (UMCR) is accessible in supervisor mode only.
Freescale Semiconductor
HRESET
HRESET
1
Access
Field STOP
Field
Addr
S = Supervisor mode only; T = Test mode only
S/T
—
S
UIMB Module Configuration Register (UMCR)
MSB
1
16
0
0
0x30 7F94 — 0x30 7F9F Reserved
IRQMUX
17
1
Base Address
00
0x30 7F90
0x30 7FA0
Figure 12-7. UIMB Module Configuration Register (UMCR)
18
2
Table 12-5. UIMB Interface Register Map (continued)
HSPEED
19
1
3
MPC561/MPC563 Reference Manual, Rev. 1.2
UIMB Test Control Register (UTSTCREG)
Reserved
Pending Interrupt Request Register (UIPEND)
See
descriptions.
20
4
Section 12.5.3, “Pending Interrupt Request Register
21
5
0000_0000_0000_0000
22
6
0x30 7F80
23
7
—
24
8
0000_0000_0000
Register
25
9
—
10
26
U-Bus to IMB3 Bus Interface (UIMB)
11
27
12
28
(UIPEND)” for bit
13
29
14
30
LSB
15
31
12-7