MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 424

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Memory Controller
10.6
The dual mapping feature also enables mapping of external memory to alternative memory regions
controlled by the memory controller. When dual mapping is enabled and an external address matches a
10-26
Dual Mapping of an External Flash Region
MPC5xx Memory Map
The default state is to allow dual-mapping data accesses only; this means
that dual mapping is possible only for data accesses on the internal bus.
Also, the default state takes the lower 2 Mbytes of the MPC563 internal
Flash memory. Hence, caution should be taken to change the dual-mapping
setup before the first data access. Dual mapping is not supported for an
external master when the memory controller serves the access; in such a
case, the MPC561/MPC563 terminates the cycle by asserting TEA.
Dual Mapping
External CSx
Flash
Figure 10-19. Aliasing Phenomenon Illustration
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
CSx
Physical External Memory
Dual-Map region
Freescale Semiconductor