MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 46

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

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Figure
Number
Example of External Multiplexing ......................................................................................... 13-6
Module Configuration Register (QADCMCR) ...................................................................... 13-8
QADC Interrupt Register (QADCINT) ................................................................................ 13-12
Interrupt Levels on IRQ with ILBS ...................................................................................... 13-13
Control Register 0 (QACR0) ................................................................................................ 13-15
Control Register 2 (QACR2) ................................................................................................ 13-18
Status Register 0 (QASR0) ................................................................................................... 13-21
QADC64E Queue Status Transition ..................................................................................... 13-26
Status Register 1 (QASR1) ................................................................................................... 13-27
QADC64E Conversion Queue Operation............................................................................. 13-28
Conversion Command Word Table (CCW) ......................................................................... 13-30
Right Justified, Unsigned Result Format (RJURR).............................................................. 13-33
Left Justified, Signed Result Format (LJSRR) ..................................................................... 13-33
Left Justified, Unsigned Result Register (LJURR) .............................................................. 13-33
QADC64E Analog Subsystem Block Diagram .................................................................... 13-34
Conversion Timing ............................................................................................................... 13-35
Bypass Mode Conversion Timing ........................................................................................ 13-36
QADC64E Queue Operation with Pause.............................................................................. 13-39
QADC64E Clock Subsystem Functions ............................................................................... 13-48
QADC64E Clock Programmability Examples ..................................................................... 13-50
Bus Cycle Accesses .............................................................................................................. 13-53
CCW Priority Situation 1...................................................................................................... 13-56
CCW Priority Situation 2...................................................................................................... 13-56
CCW Priority Situation 3...................................................................................................... 13-57
CCW Priority Situation 4...................................................................................................... 13-57
CCW Priority Situation 5...................................................................................................... 13-58
CCW Priority Situation 6...................................................................................................... 13-58
CCW Priority Situation 7...................................................................................................... 13-59
CCW Priority Situation 8...................................................................................................... 13-59
CCW Priority Situation 9...................................................................................................... 13-60
CCW Priority Situation 10.................................................................................................... 13-60
CCW Priority Situation 11.................................................................................................... 13-61
CCW Freeze Situation 12 ..................................................................................................... 13-61
CCW Freeze Situation 13 ..................................................................................................... 13-62
CCW Freeze Situation 14 ..................................................................................................... 13-62
CCW Freeze Situation 15 ..................................................................................................... 13-62
CCW Freeze Situation 16 ..................................................................................................... 13-62
Port
Port A Data Direction Register (DDRQA) .......................................................................... 13-14
Control Register 1 (QACR1) ............................................................................................... 13-16
x
Data Register (PORTQA and PORTQB).................................................................. 13-13
MPC561/MPC563 Reference Manual, Rev. 1.2
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