MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 242

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

System Configuration and Protection
Figure 6-1
6-2
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•
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Periodic Interrupt Timer
timer to generate periodic interrupts for use with a real-time operating system or the application
software. The PIT provides a period from 1 µs to 4 seconds with a four-MHz crystal or 200 ns to
0.8 ms with a 20-MHz crystal. The PIT function can be disabled.
Software Watchdog Timer
asserts a reset or non-maskable interrupt, as selected by the system protection control register
(SYPCR), if the software fails to service the SWT for a designated period of time (e.g., because the
software is trapped in a loop or lost). After a system reset, this function is enabled with a maximum
time-out period and asserts a system reset if the time-out is reached. The SWT can be disabled or
its time-out period can be changed in the SYPCR. Once the SYPCR is written, it cannot be written
again until a system reset.
Freeze Support
SWT, PIT, TB, DEC, and RTC should continue to run during freeze mode.
Low Power Stop
timers are frozen but others are not.
shows a block diagram of the system configuration and protection logic.
(Section 6.1.11, “Freeze
(Section 6.1.12, “Low Power Stop
(Section 6.1.9, “Periodic Interrupt Timer
MPC561/MPC563 Reference Manual, Rev. 1.2
(Section 6.1.10, “Software Watchdog Timer
Operation”)—The SIU allows control of whether the
Operation”)—In low power modes, specific
(PIT)”)—The SIU provides a
(SWT)”)—The SWT
Freescale Semiconductor