MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1228

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Electrical Characteristics
F.7
The characteristics found in this section apply only to the MPC563.
Note: (V
Note: (V
F-12
1
2
3
4
1
2
3
Array and CENSOR Data
Typical program and erase times assume nominal supply values and 25 °C.
Erase time specification does not include pre-programming operation
Word size is 32 bits.
The maximum hardware programming time of the entire Flash (not including the shadow row) is 20 µs x (512 Kbytes
/ 4 bytes per word), or 131,072 words, (no software overhead).
A Program/Erase cycle is defined as switching the bits from 1 to 0 to 1.
A CENSOR Set/Clear cycle is defined as switching the bits from 1 to 0 to 1.
Maximum total time @ 150 °C junction temperature ≤ 1 year.
1
2
CENSOR Set/Clear
DDF
DDF
T
Array P/E Cycles
Symbol
T
T
Typical set and clear times assume nominal supply values and 25 °C.
Clear time specification does not include pre-set operation.
ERASEM
ERASE
PROG
Flash Electrical Characteristics
Symbol
= 2.6 V ± 0.1 V, V
= 2.6 V ± 0.1 V, V
T
Retention
Symbol
Cycles
CLEAR
T
SET
2
Block Erase Time
Module Erase Time
Word Programming Time
1
Table F-7. CENSOR Cell Program and Erase Characteristics
FLASH
FLASH
Maximum number of Program/Erase cycles per block to guarantee
data retention.
Minimum number of Program/Erase cycles per bit before failure.
Minimum data retention at an average of 85 °C junction temperature.
Minimum data retention at an average of 125 °C junction temperature.
Table F-6. Array Program and Erase Characteristics
CENSOR Bit Clear Time
= 5.0 V ± 0.25 V, T
= 5.0 V ± 0.25 V, T
CENSOR Bit Set Time
MPC561/MPC563 Reference Manual, Rev. 1.2
Meaning
2
2
Meaning
Table F-8. Flash Module Life
3,4
A
A
= T
= T
2
L
L
Meaning
to T
to T
H
H
, T
, T
Minimum
B
B
= T
= T
Minimum
L
L
to T
to T
H
H
)
)
Typical
Typical
Value
Value
115
13
15
13
3
1
1
Maximum
Maximum
250
60
Freescale Semiconductor
12
60
20
Min 15 years
Min 10 years
Value
1,000
100
Units
µs
s
Units
µs
s
s
3
3