EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 189

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

DS785UM1
7.3.7 Hardware Cursor
7.4 Functional Details
brightness control. The Bright output signal can also be used for direct pulse width modulated
CCFL brightness control that can be synchronized to the display frame rate.
The Raster Engine provides hardware cursor support. The cursor size is programmable up to
64 pixels wide by 64 pixels in height. The cursor is stored anywhere in memory as a 2 bpp
image. The 2 bpp image pixel information implies transparent, inverted, cursor color 1, or
cursor color 2. The cursor hardware must be supplied this information:
Using this information, the hardware overlays the cursor in the output video stream. Bottom
and right edge clipping is performed by hardware. Some extra calculations and register
setups are required for cursor support during dual scan display mode.
The Raster Engine’s block diagram is shown in
several major sections; VILOSATI, video FIFO, pixel mux, blink logic, color LUT, RGB mux,
output shift logic, grayscale circuitry, hardware cursor logic, YCrCb encoder, and video timing
section. A video stream signature generator is also included for built in self testing.
• Image starting address
• Two cursor colors
• An X screen location and a Y screen location
• A cursor size
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
Figure
7-1. The video pipeline consists of
EP93xx User’s Guide
7-7
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