EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 693
![IC ARM9 SOC PROCESSOR 208LQFP](/photos/12/23/122385/mfg_ep9302_parts_sml.jpg)
EP9302-CQZ
Manufacturer Part Number
EP9302-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9302-IQZ.pdf
(42 pages)
3.EP9302-IQZ.pdf
(4 pages)
4.EP9302-IQZ.pdf
(40 pages)
Specifications of EP9302-CQZ
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Data Ram Size
16 bit
Interface Type
USB, USART, SPI
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
37
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1137
Available stocks
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Part Number:
EP9302-CQZ
Manufacturer:
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Quantity:
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EP9302-CQZ
Manufacturer:
ALTERA
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- EP9307-CRZ PDF datasheet
- EP9302-IQZ PDF datasheet #2
- EP9302-IQZ PDF datasheet #3
- EP9302-IQZ PDF datasheet #4
- Current page: 693 of 824
- Download datasheet (13Mb)
DS785UM1
22.2.2.4 GPIOTXCOMPLETE
22.2.2.5 SLOT2INT
22.2.2.6 SLOT1TXCOMPLETE
22.2.2.7 SLOT2TXCOMPLETE
22.3 System Loopback Testing
22.4 Registers
The transmit GPIOTXCOMPLETE interrupt is asserted when all values written to the
AC97S12Data have been transmitted. It is cleared when any data is written to the
AC97S12Data.
The receive SLOT2INT interrupt is asserted when the AC97S2Data register has new data
that has not been read. By reading the data in the AC97S2Data register the SLOT2INT
interrupt is cleared.
The transmit SLOT1TXCOMPLETE interrupt is asserted when all values written to the
AC97S1Data have been transmitted. It is cleared when any data is written to the
AC97S1Data.
The transmit SLOT2TXCOMPLETE interrupt is asserted when all values written to the
AC97S2Data have been transmitted. It is cleared when any data is written to the
AC97S2Data.
A loopback test mode is available for system testing so that data transmitted on SDATAOUT
can also be received on SDATAIN. Loopback mode is entered when a “1” is written to the
LOOP bit in AC97GCR register. For normal operation the LOOP bit must always be “0”,
which is also the default state at reset.
Note: For this test mode to work, an external bit clock will need to be supplied.
0x8088_000C
0x8088_001C
0x8088_002C
0x8088_0000
0x8088_0004
0x8088_0008
0x8088_0010
0x8088_0014
0x8088_0018
0x8088_0020
0x8088_0024
0x8088_0028
Address
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Type
Read
Read
Read
Read
-
Table 22-2. AC’97 Register Memory Map
Copyright 2007 Cirrus Logic
AC97RXCR1
AC97RXCR2
AC97TXCR1
AC97TXCR2
AC97RISR1
AC97ISR1
AC97DR1
AC97SR1
AC97DR2
AC97SR2
AC97IE1
Name
-
Data read or written from/to FIFO1
Control register for receive
Control register for transmit
Status register
Raw interrupt status register
Interrupt Status
Interrupt Enable
Reserved
Data read or written from/to FIFO2
Control register for receive
Control register for transmit
Status register
Description
EP93xx User’s Guide
AC’97 Controller
22-5
22
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