EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 214

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

7
7-32
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7.4.10.2 PixelMode
7.4.11 Blink Logic
7.4.11.1 BlinkRate
7.4.11.2 Defining Blink Pixels
Pixel data is transferred from the FIFO to the Video Pixel Mux two 32-bit words at a time (total
of 64 bits). Bits[2:0] of the
11. The Video Pixel MUX uses the
contained in the 64 bits of data. The Video Pixel Mux extracts pixel data from the 64-bits and
passes that pixel data to the BLINK logic one pixel at a time.
The blink logic facilitates blinking of individual pixels as they move through the video pipeline.
The blink frequency is controlled by the
same rate.
This value is used to control the number of video frames that occur before the pixel value that
is assigned to blink is switched between its non-blinked and blinked values. The actual rate is
calculated by:
Blink cycle = 2 x (1 / VCLK) x HClkTotal x VLinesTotal x (255 - BlinkRate)
A blink pixel must be defined before the blink logic is applied to a given pixel. The
“BlinkPattrn”
Note: All other combinations for these three bits are illegal.
bit P2
where:
VCLK is the basic clock rate of the video logic
HClkTotal is the value contained in the
VLinesTotal is the value contained in the
BlinkRate is the value contained in the
0
0
0
1
1
and
VLineStep = 640 x 4bpp/32
“PattrnMask”
bit P1
0
0
1
0
1
Table 7-11. Bits P[2:0] in the PixelMode Register
“PixelMode”
Copyright 2007 Cirrus Logic
bit P0
registers are used to define the blink pixels.
0
1
0
0
0
“PixelMode”
register specify the pixel depth as shown in
“BlinkRate”
Pixel Multiplexor disabled
4 bits per pixel
8 bits per pixel
16 bits per pixel
24 bits per pixel
“HClkTotal”
“BlinkRate”
register to determine how many pixels are
“VLinesTotal”
register. All blinking pixels blink at the
Function
register
register
register
DS785UM1
Table 7-