EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 401
![IC ARM9 SOC PROCESSOR 208LQFP](/photos/12/23/122385/mfg_ep9302_parts_sml.jpg)
EP9302-CQZ
Manufacturer Part Number
EP9302-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9302-IQZ.pdf
(42 pages)
3.EP9302-IQZ.pdf
(4 pages)
4.EP9302-IQZ.pdf
(40 pages)
Specifications of EP9302-CQZ
Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Data Ram Size
16 bit
Interface Type
USB, USART, SPI
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
37
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1137
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
EP9302-CQZ
Manufacturer:
Cirrus
Quantity:
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EP9302-CQZ
Manufacturer:
ALTERA
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20 000
- EP9307-CRZ PDF datasheet
- EP9302-IQZ PDF datasheet #2
- EP9302-IQZ PDF datasheet #3
- EP9302-IQZ PDF datasheet #4
- Current page: 401 of 824
- Download datasheet (13Mb)
DS785UM1
10.1.9 Internal M2P/P2M DMA Functional Description
10.1.9.1 Internal M2P/P2M DMA Buffer Control Finite State Machine
The data received on each of the five peripheral receive DMA Rx Data buses is transferred
into an internal receive packer unit. The packer unit is used to convert the byte-wide data
received from the peripheral into words to be transferred over the system bus to the memory.
The packer unit stores 4 words (one quad-word) of data, which is the size of the burst
transfers to and from memory over the system bus. Provision for the memory access latency
is provided by FIFOs within the peripheral. The size of the FIFOs can be selected as
appropriate for the data rate generated by the peripheral.
Transmit data is fetched from system memory by the AHB master interface and placed into
the transmit un-packer. The transmit un-packer converts the quad-word burst of DMA data
into byte data for transmission over the transmit peripheral DMA bus. The transmit un-packer
contains 4 words (one quad-word) of storage. Additional latency is provided by FIFOs within
the peripheral, the size of which can be selected as appropriate for the peripheral.
The number of data transfers over the peripheral DMA bus (that is, the number of bytes) are
counted by packer/un-packer unit. If the number of bytes transferred reaches the
MaxTransfer count, the appropriate RxTC/TxTC signal is asserted causing the flush to
memory of data from a packer unit, and the invalidation of any data remaining in an un-
packer unit.
Each DMA internal M2P/P2M channel is controlled by a finite state machine (FSM) which
determines whether the channel is transferring data, and whether it is currently generating an
interrupt.
Write
Base Address
DMA_NEXT
DISABLE
CE.ABORT.ICE
Figure 10-1. DMA M2P/P2M Finite State Machine
CE.ICE.ABORT
Buffer End or
Copyright 2007 Cirrus Logic
DISABLE
DMA_IDLE
DMA_ON
Buffer End or
DISABLE
CE.ICE
ENABLE
DMA_STALL
Write Base
Address
EP93xx User’s Guide
DMA Controller
10-7
10
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